AnsweredAssumed Answered

How to control tDQS, tDQ & etc. timing parameters in DDR initialization script ?

Question asked by Peter Amond on Apr 19, 2018
Latest reply on Apr 19, 2018 by Yuri Muhin

Hi All,

Dear Wang Lin

 

 

This is a custom hardware design with;

Processor - iMAX6Q - MCIMX6Q6AVT10AC

RAM - 933MHz Micron DDR3L - MT41K256M16TW-107 IT:P

 

1) Here is the configuration for the script. Can you check and tell me the configurations are correct or not ?

 

 

2) Don't you have different script generator for DDR3L type memories (Low Power RAM) ? 

3) In memory type I don't have to select DDR3L-933 option. What should I select ?

4) In DRAM clock frequency I don't have to select any option for 933MHz. What should I select ?

5) Under SI configuration section what should I select for 

DRAM DSE Setting - DQ/DQM (ohm)

DRAM DSE Setting - ADDR/CMD/CTL (ohm)

....etc.

6)  If I couldn't control impedance of single ended and DATA signals of DDR layout any method to control timing in while calibration process?

 

Can you give me an idea on this SI configuration parameters. Under which conditions of the memory should we change those values and how ?

 

Waiting for a detailed explanation for this. 

 

Regards & Thanks,

Peter.

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