I want to ask the workaround for e8052.
It is described at 184.108.40.206 Internal RMII reference clock in VYBRIDHDUG Rev.1.
I want to confirm the workaround based on "EXTERNAL CLOCK SOURCE" scheme.
Can I select the CKO1 or CKO2 pin for the clock_Out pin(Fig42)?
Are there any problem to select the PLL5 for clock source of the clock_Out(Fig42)?