AnsweredAssumed Answered

DMA interrupt on Major Loop complete without the XFER_DONE bit being set

Question asked by Cash Reuser on Apr 13, 2018
Latest reply on Apr 24, 2018 by Carlos_Musich

Hello,

 

I am working with the EDMA on the MIMXRT1050-EVK prior to getting in our hardware.

 

I have created a couple of arrays and use memory2memory transfers to mimic what our hardware would send to us via the SPI ports. I have 2 files to mimic 2 devices and trigger a transfer using the PIT timer though the XBAR.

 

It seems that when the DMA requests occur within a microsecond of each other I will get an interrupt but the XFER_DONE in the CSR is not set. About every 1.1 seconds I get 3 interrupts without the XFER_DONE being set.

 

I have set one PIT to 10 us, and the other to 11 us...if I set them both to 10, I will not get any XFR_DONE bit set on the second channel, but every interrupt will occur.

 

Does anyone know why this would happen? I can't seem to find anything in documentation on this.

 

Regards,

 

Cash

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