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What Should be The Impedance of DATA & Single Ended Signals of DDR Memory Layout ?

Question asked by Peter Amond on Apr 12, 2018
Latest reply on Apr 12, 2018 by igorpadykov

Dear All,

 

This is regarding iMAX6Q processor based hardware design which is similar to Nitrogen6_MAX boundary devices development board.

 

In DDR memory layout I am using 100 Ohms impedance control for differential pair signals and what should be the impedance for the other signals like Data and ODT single ended signals ? Is that okay to use 50 Ohms or 80 Ohms ?

 

1) Differential Pair 100 Ohms

DRAM_CLK0_P

DRAM_CLK0_N

...etc

 

2) Data Signals; What should be the impedance ?

DRAM_D1

DRAM_SDODT0

....etc

 

I must be thankful to you if you can give me an idea on this as soon as possible.

 

Regards.

Peter.

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