AnsweredAssumed Answered

SGTL5000 Routing LINEIN -> ADC -> DAP -> DAC -> HP_OUT

Question asked by Tak Ming Marco Pang on Apr 11, 2018
Latest reply on Apr 17, 2018 by Tak Ming Marco Pang

G'day!oing

 

Recently decided to give this another go, as my previous attempt to use the SGTL5000 with the k70 TWR module.
I have tried to route from LineIn to HP_Out, that is working fine, so my I2C module is functioning correctly.
SGTL5000 Routing

 

However! Going next step and I tried configure the codec to use the ADC, DAP and DAC in between LineIn and HP_OUT. Only for it to be completely silent with an initialisation "pop" instead.
I have tried unmuting the ADC, DAP and DAC but they did not seem to fix the problem of no sound coming through.
My understanding is the DAP's subblocks "can be individually disabled" (Page 20 of the SGTL5000 Datasheet) and passes the signal along without modification.
In my code, I have disabled these sub-blocks (Mixer, AVC, Surround, Bass) and disabled the PEQ filter. 
DAP block diagram

void SGTL5000_Init(void)

{

 

//--------------- Power Supply Configuration----------------

SGTL_WriteRegister(SGTL5000_CHIP_LINREG_CTRL, 0x0008);

// SGTL5000_CHIP_LINREG_CTRL, Configure VDDD level to 1.2V (bits 3:0)

 

SGTL_WriteRegister(SGTL5000_CHIP_ANA_POWER, 0x7260);

// SGTL5000_CHIP_ANA_POWER, Power up internal linear regulator (Set bit 9)


SGTL_WriteRegister(SGTL5000_CHIP_ANA_POWER, 0x4260);

// setting VDDD to externally driven, @Page 26/68 of SGTL Initialisation 0x4260


SGTL_WriteRegister(SGTL5000_CHIP_LINREG_CTRL, 0x006C); // SGTL5000_CHIP_LINREG_CTRL, Charge pump to use the VDDIO rail (set bit 5 and bit 6).


//------ Reference Voltage and Bias Current Configuration----------

//NOTE: VDDA voltage value dependent writes
SGTL_WriteRegister(SGTL5000_CHIP_REF_CTRL, 0x004E);

// SGTL5000_CHIP_REF_CTRL, Setting Ground, ADC, DAC ref VAG_VAL = VDDA/2 @1.8/2 = 0.9, datasheet suggest ~= 1.575 | BIAS_CTRL @ -50% | Last bit E or F is to prevent Pop


SGTL_WriteRegister(SGTL5000_CHIP_LINE_OUT_CTRL, 0x0322);

// SGTL5000_CHIP_LINE_OUT_CTRL, Setting LINEOUT ref voltage to VDDIO/2 (1.65V)


//------ Other Analog Block Configurations----------

//NOTE: VDDA voltage value dependent writes
SGTL_WriteRegister(SGTL5000_CHIP_REF_CTRL, 0x004F);

// SGTL5000_CHIP_REF_CTRL, Configure slow ramp up rate to minimize pop (bit 0)


SGTL_WriteRegister(SGTL5000_CHIP_SHORT_CTRL, 0x1106);

// SGTL5000_CHIP_SHORT_CTRL, Enable short detect mode for headphone left/right/centre @ 75mA


SGTL_WriteRegister(SGTL5000_CHIP_ANA_CTRL, 0x0133);

// SGTL5000_CHIP_ANA_CTRL, Enable Zero-cross detect if needd for HP-OUT (bit 5) and ADC (bit 1)


//----------------Power up Inputs/Outputs/Digital Blocks-------------------
SGTL_WriteRegister(SGTL5000_CHIP_ANA_POWER, 0x6AFF);

//SGTL5000_CHIP_ANA_POWER, Power up LINEOUT, HP, ADC, DAC


SGTL_ModifyRegister(SGTL5000_CHIP_DIG_POWER, 0xFFBF, 0x1 << 6);

//SGTL5000_CHIP_DIG_POWER, Power up digital block DAP_POWERUP (bit 4)


SGTL_ModifyRegister(SGTL5000_CHIP_DIG_POWER, 0xFFDF, 0x1 << 5);

//SGTL5000_CHIP_DIG_POWER, Power up digital block DAC_POWERUP (bit 5)


SGTL_ModifyRegister(SGTL5000_CHIP_DIG_POWER, 0xFFEF, 0x1 << 4);

//SGTL5000_CHIP_DIG_POWER, Power up digital block ADC_POWERUP (bit 6)


SGTL_ModifyRegister(SGTL5000_CHIP_DIG_POWER, 0xFFFD, 0x1 << 1);

//SGTL5000_CHIP_DIG_POWER, Power up digital block I2S_OUT_POWERUP(bit 1)


SGTL_ModifyRegister(SGTL5000_CHIP_DIG_POWER, 0xFFFE, 0x1 << 0);

//SGTL5000_CHIP_DIG_POWER, Power up digital block I2S_IN_POWERUP (bit 0)


//--------------------Set MCLK and Sample Clock----------------------
SGTL_ModifyRegister(SGTL5000_CHIP_CLK_CTRL, 0xFFC8, (0x1 << 2));

//Configure SYS_FS clock to 44.1kHz

 

SGTL_ModifyRegister(SGTL5000_CHIP_CLK_CTRL, 0xFFFC, (0x0 << 0));

//Setting MCLK_FREQ [0] to 256*Fs = 0x0, 0x1 = 384*Fs, 0x2 = 512*Fs, 0x3 = Use PLL

 

SGTL_ModifyRegister(SGTL5000_CHIP_I2S_CTRL, 0xFF7F, (0x1 << 7));

//Setting I2S to Master [7]


//--------------------Set I/o Routing--------------------------------

 

/* LINEIN -> ADC */
SGTL_ModifyRegister(SGTL5000_CHIP_ANA_CTRL, 0xFFFB, (0x1 << 2));

//Setting [2] SELECT_ADC to 0x0 for LINEIN

 

 

/* [LINEIN -> ADC] -> DAP -> DAC -> HP_OUT */
//Note: [LINEIN -> ADC] should be set
SGTL_ModifyRegister(SGTL5000_CHIP_SSS_CTRL, 0xFCFF, (0x0 << 8));

//Setting [9:8] DAP_SELECT to 0x0 for DAP mixer, ADC set as source for DAP mixer


SGTL_ModifyRegister(SGTL5000_CHIP_SSS_CTRL, 0xFF3F, (0x0 << 6));

//Setting [7:6] DAP_SELECT to 0x0 for ADC, ADC set as source for DAP


SGTL_ModifyRegister(SGTL5000_CHIP_SSS_CTRL, 0xFFCF, (0x3 << 4));

//Setting [5:4] DAC_SELECT to 0x3 for DAP, DAP set as source for DAC


SGTL_ModifyRegister(SGTL5000_CHIP_ANA_CTRL, 0xFFBF, (0x0 << 6));

//Setting [6] SELECT_HP to 0x0 for DAC, As DAC set as source of HP

 

//---------------- Digital Audio Processor Configuration----------------

// NOTE: DAP will be in a pass-through mode if none of DAP sub-blocks are enabled
SGTL_ModifyRegister(SGTL5000_DAP_CONTROL, 0xFFFE, (0x1 << 0));

//Enable DAP_EN [0] - DAP block


SGTL_ModifyRegister(SGTL5000_DAP_CONTROL, 0xFFEF, (0x0 << 4));

//Disable MIX_EN [4] - Digital Mixer Sub-block


SGTL_ModifyRegister(SGTL5000_DAP_AVC_CTRL, 0xFFFE, (0x0 << 0));

//Disable AVC_EN [0] - Automatic Volume Control Sub-block


SGTL_ModifyRegister(SGTL5000_DAP_SGTL_SURROUND, 0xFFFE, (0x0 << 0));

//Disable SELECT [1:0] - Freescale Surround Selection Sub-block


SGTL_ModifyRegister(SGTL5000_DAP_BASS_ENHANCE, 0xFFFE, (0x0 << 0));

//Disable BASS_EN [0] - Freescale Base Enhance Sub-block


SGTL_WriteRegister(SGTL5000_DAP_AUDIO_EQ, 0x0);

 

//---------------- Input Volume Control---------------------
SGTL_WriteRegister(SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000);

//Setting Volume to 0dB gain from ADC


//---------------- Volume and Mute Control---------------------
SGTL_WriteRegister(SGTL5000_CHIP_ANA_HP_CTRL, 0x7F7F);

// Configure HP_OUT left and right volume to minimum -51.5dB, unmute HP_OUT and ramp volume up to desire volume.


SGTL_WriteRegister(SGTL5000_CHIP_ANA_HP_CTRL, 0x1818);

//Set to 0dB gain // Configure HP_OUT left and right volume to 0dB

 

SGTL_ModifyRegister(SGTL5000_CHIP_ANA_CTRL, 0xFFDF, (0x1 << 5));

//Enable Zero Detect [5]


SGTL_ModifyRegister(SGTL5000_CHIP_ANA_CTRL, 0xFFEF, (0x0 << 4));

// Unmute MUTE_HP [4] (0x0 = Unmute)


SGTL_ModifyRegister(SGTL5000_CHIP_ANA_CTRL, 0xFEFF, (0x1 << 8));

// Mute MUTE_LO [8] (0x0 = Unmute)


SGTL_ModifyRegister(SGTL5000_CHIP_ANA_CTRL, 0xFFFE, (0x0 << 0));

// Unmute MUTE_ADC [0] (0x0 = Unmute)

}

The above is my initialisation for the Codec, apologies for the untidiness of the code. It is really my first time using embedded tools.
Thank you in advance! It would be lovely if someone can point me the right direction.

 

EDIT: I solved the problem. I did not see the DAC needed to be unmuted. I feel silly but at least everything works now!

Outcomes