PCIe switch enumeration using LS1046

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PCIe switch enumeration using LS1046

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xabiven
Contributor II

Hello all,

I am working on a custom LS1046 board where the processor is attached to an embedded PCIe switch. The LS1046 is configured as root complex, and is in charge of the whole PCIe bus enumeration.

Issue description

Under UBoot, the enumeration process works fine, and we can discover all PCIe devices. Read and write accesses are possible into the various PCIe devices.

Nevertheless, this enumeration process cause an AXI slave error which crash the Linux Kernel at startup when unmasking interrupts.

Error propagation process:

1) The LS1046 enumerate PCIe bus, and use type 1 configuration requests to discover the PCIe buses behind the switch

2) Enumerating these buses cause the PCIe switch to forward an "unsupported request" to the LS1046 PCIe controller when scanning ports without endpoint devices (this is a correct switch's behavior)

3) The PCIe controller set the "Received master abort" bit when receiving the unsupported request (UR) (RMA bit is set to '1' in 0x1E register)

4) Then, we observe that the ISR_EL1[1:0] bits are set to 0b10, and ESR_EL1 indicates a "System error\slave error"

The behavior is similar under Linux when enumerating the bus, but the CPU directly crash because interrupts are already unmasked.

Important remark: It is possible to enumerate the bus using a T2080 or a T1042 processor without crashing the LInux. The "unsupported request" is also send to the CPU but these models doesn't take it into account as a system error.

=> Is it possible to stop the error propagation ?

=> Do you have an enumeration exemple of a PCIe bus including a switch using a LS1046 CPU?

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xabiven
Contributor II

Dear Yiping,

Indeed, our problem was related to A-008822 erratum : we were patching the registers directly through the PBL instructions during CPU startup (as recommended in the errata document).

Now, we suppressed instructions from the PBL, and the LS1046A starts with its default configuration. So, the full enumeration is performed without returning the AXI slave error. Then, the register's patch recommended in the erratum is applied by Linux Kernel after its PCIe enumeration.

Best regards,

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xabiven
Contributor II

Dear Yiping,

Indeed, our problem was related to A-008822 erratum : we were patching the registers directly through the PBL instructions during CPU startup (as recommended in the errata document).

Now, we suppressed instructions from the PBL, and the LS1046A starts with its default configuration. So, the full enumeration is performed without returning the AXI slave error. Then, the register's patch recommended in the erratum is applied by Linux Kernel after its PCIe enumeration.

Best regards,

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yipingwang
NXP TechSupport
NXP TechSupport

Hello xabiven,

Which version LSDK are you using now?

Please check whether this Linux Kernel patch [2/2] pci/layerscape: change the default error response behavior - Patchwork  has already been applied in your source code as a workaround.


Have a great day,
TIC

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