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i.MX6ULL VDD_ARM_CAP voltage changes

Question asked by Chad Wolter on Apr 11, 2018
Latest reply on Apr 20, 2018 by Chad Wolter

Please see attached oscilloscope capture of the VDD_ARM_CAP (LDO_ARM) pin in a custom i.MX6ULL design.  As can be seen, the voltage of this rail, which is nominally supposed to be 1.15VDC, is changing its voltage regularly.  This is occurring when our Linux kernel boots and after it has been running.  Per the i.MX6ULL reference guide (version 11/2017), section 39.2, would the output in the attached scope capture be consistent with behavior if the device was in "Power Gate" mode? 


Per the Reference manual, section 39.2, there are 3 modes for the Digital LDOs

1. Power Gate

2. Analog regulation

3. Bypass


Looking now at section 39.6.4 (PMU_REG_COREn definition), in the REG0_TARG field, would the following settings map to the modes above?


1.  REG0_TARG = 0b00000 -> Analog Regulation

2.  0b00001 <= REG0_TARG <= 0b11110 -> Power Gate, with voltage setting per the register value

3. REG0_TARG = 0b11111 -> Bypass


Further, how do I set these modes in Linux?  I am looking to do this WITHOUT using the API function calls referenced in Chapter 26 of the Linux Reference manual.  I have looked in the device tree included with the version 4.9.11 Linux release from NXP (imx6ull.dtsi), but I do not see any setting in the anatop regulator definition that would correspond to the REG0_TARG bits of the PMU_REG_COREn register:


reg_arm: regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <24>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;


Further, I have looked in the /sys/devices/soc0/soc/2000000.aips-bus/20c8000.anatop directory on a running version of the kernel, and I cannot find any settings there either to touch this register.


Please help me solve this issue, or at least explain why I am seeing the core voltage change


kind regards

Chad Wolter