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i.MX6Q SABRE SDP/B DDR3 Register Programming Aid

Question asked by HIROYUKI SUZUKI on Apr 5, 2018
Latest reply on Apr 5, 2018 by Yuri Muhin

Please tell me  about the question.

 

He recommended setting value is 1.
Why is this?

DRAM_Data is single-end signals.
So I think it is "CMOS input type" setting.

 

 IOMUXC_SW_PAD_CTL_GRP_DDRMODE

  

  bit17 DDR_INPUT
   DDR / CMOS Input Mode Field
   Select one out of next values for group: DDRMODE (Pads: DRAM_D[63:0]).
    0: CMOS input type
    1: Differential input mode (recommended)"

 

Best regards,

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