This is regarding i.MAX6Q based custom hardware design and I'm having timing margin issues in I/O interface between chipset and dram. If I/O interface margin is poor by routing issue or layout, it may cause failure depending on noise pattern ( different application make different noise level). So to solve this issue what do you suggest ?
1) Can we do this using chipset design option to control this kind of timing like phase shift for tDQS and tDQ.? Can you explain how to do this ?
2) Is it possible to down operating frequency ( ex 2400Mbps --> 2133Mbps ) How can we do this in uboot level ?
3) If it is related to clock timing, We can add capacitance or change termination resistance on CLK and CLK/. To do this what we should do ? Which parameter should I change in DDR initialization script before do memory calibration ?