I have read the Error Correcting Codes Implemented on MPC5744P (Rev. 0, Draft B,12/2017) which was written by you earlier. I have some doubts about ECC & EDC. Could you answer my questions?
1. How to generate the ECC checkbits
There is no detail introduction about the implement of ECC algorithm in RM or Error Correcting Codes Implemented on MPC5744P. I mean how to generate the ECC check bits was not clarified. Is ECC algorithm similar to Parity check?
2. The difference between e2eECC and ECC.
As described in RM Table 3-1. ECC comparison of data write then read sequence, the e2eECC checkbits which is provided by master include coverage of address and data information, while the ECC check-bits which is provided by slave memory include data information only?
3. The function of EDC
“in most cases it is additional EDC protection (supervision), checksum being added and subsequently removed from/to data, address, attribute or other signals, according the specific needs of protected transfer or memory module. It is further protection capable to find ECC malfunction”.
Is EDC an algorithm for check the ECC correction logic? But how to check? By decoding ECC?
By the way, does SRAM has EDC?
4. ECC manipulation / ECC re-coded
Why is ECC re-coded due to removing of address portion from transferred packet address, data, e2eECC. I mean why does the address portion need to remove from the full ECC?
And how? By EDC?
I am looking for forward to hear from you.