MPC8548 Uboot InstructionTLBError

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MPC8548 Uboot InstructionTLBError

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systick
Contributor II

Hi all,

I working on Uboot for the MPC8548,

-I built the Uboot with ppc_85xx- toolchain,
-The Entry Point Address of elf file is 0xfffa0000,
- My Memory map is ;

   0x0000_0000 | 256MB | 0x0FFF_FFFF | DDR SDRAM
   0x5000_0000 | 64MB | 0x53FF_FFFF | PCI 1 Prefetchable Memory
   0x5400_0000 | 64MB | 0x57FF_FFFF | PCI 1 Non-Prefetchable Memory
   0x5800_0000 | 64MB | 0x5BFF_FFFF | PCI 1 IO
   0x6000_0000 | 64MB | 0x63FF_FFFF | PCI Express Prefetchable Memory
   0x6400_0000 | 64MB | 0x67FF_FFFF | PCI Express Non-Prefetchable Memory
   0x6800_0000 | 64MB | 0x6BFF_FFFF | PCI Express IO
   0xF8B0_0000 | 16MB | 0xF7FF_FFFF | NVRAM/CADMUS
   0xF000_0000 | 64MB | 0xFBFF_FFFF | LBC SDRAM
   0xE000_0000 | 1MB | 0xFE0F_FFFF | Configuration Control Registers
   0xD000_0000 | 64MB | 0xD3FF_FFFF | SODIMM Flash
   0xFF80_0000 | 8MB | 0xFFFF_FFFF | Boot Flash

After the install program to board, program stay at 0xfffff290 address, I did comparison with elf file, its InstructionTLBError.

How can I fix this, I need suggestions. 

I look forward to your replies.

Your Sincerely.

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2 Replies

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alexander_yakov
NXP Employee
NXP Employee

Instruction TLB error means - "Virtual addresses associated with an instruction fetch do not match any valid TLB entry."

That is - an attempt to fetch some instruction from some address caused this error, because this particular address is not configured in TLB. Typically this means either TLB configuration issue or attempt to execute code from some invalid location.

When TLB error interrupt is taken, register SRR0 is set to the effective address of the instruction causing the instruction TLB error interrupt.

For more details please look e500 Core Reference Manual, Section 5.7.13 "Instruction TLB Error Interrupt"

Here is a direct link to this document:

https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf


Have a great day,
Alexander
TIC

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systick
Contributor II

Hi Mr.Yakovlev,

Thanks for the reply, I will focus on SRRx registers.

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