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MPC5634 CAN Rx FIFO

Question asked by tongyue huang on Mar 28, 2018

Hi,

      I am using MPC5634 CAN Rx FIFO, but it stops CAN_A.RXIMR[i].R = 0x0; 

Here is my code:

 


static void FlexCANInit(uint16_t baudrate)
{
uint8_t i;

CAN_A.MCR.B.MDIS=0;
CAN_A.MCR.B.FRZ=1;
CAN_A.MCR.B.HALT=1;
CAN_A.MCR.B.FEN = 1; /* 1:Enable Rx FIFO,0:Disable Rx FIFO*/
CAN_A.MCR.B.MAXMB=64;

switch(baudrate)
{
case(250)://baud=250KHz
CAN_A.CR.B.PRESDIV=1; //baud=250KHz
CAN_A.CR.B.PSEG1=3;
CAN_A.CR.B.PSEG2=3;
CAN_A.CR.B.PROPSEG=6; //TSEG2=3 ,TSEG1=3 ,PROPSEG=6;
break;
case(500)://baud=500KHz
CAN_A.CR.B.PRESDIV=0; //baud=500KHz
CAN_A.CR.B.PSEG1=3;
CAN_A.CR.B.PSEG2=3;
CAN_A.CR.B.PROPSEG=6; //TSEG2=3 ,TSEG1=3 ,PROPSEG=6;
break;
default:
CAN_A.CR.B.PRESDIV=1; //baud=250KHz
CAN_A.CR.B.PSEG1=3;
CAN_A.CR.B.PSEG2=3;
CAN_A.CR.B.PROPSEG=6; //TSEG2=3 ,TSEG1=3 ,PROPSEG=6;
break;
}

CAN_A.CR.B.RJW=0;
CAN_A.CR.B.BOFFMSK=0;
CAN_A.CR.B.ERRMSK=0;
CAN_A.CR.B.CLKSRC=0; /* 0->OSC 8Mhz,1->bus clock */
CAN_A.CR.B.LPB=0;
CAN_A.CR.B.TWRNMSK=0;
CAN_A.CR.B.RWRNMSK=0;
CAN_A.CR.B.SMP=0;
CAN_A.CR.B.BOFFREC=0;
CAN_A.CR.B.TSYN=0;
CAN_A.CR.B.LBUF=0;
CAN_A.CR.B.LOM=0;

for(i=0;i<64;i++)
{
CAN_A.BUF[i].CS.B.CODE = 0; 
}

/* Configure MB0-7 for Rx FIFO */
for (i=0; i<8; i++)
{
CAN_A.RXIMR[i].R = 0x0; /* Receive everything */
}
CAN_A.IFRL.B.BUF05I = 1; /* Enable msg available interrupt */

 

/* Configure MB8-15 as Tx */
for (i=8; i<16; i++)
{
CAN_A.BUF[i].CS.B.CODE = 0x8; /* Set MB to TX INACTIVE */
CAN_A.BUF[i].CS.B.SRR = 0x1; /* Set SRR to be recessive */
CAN_A.IMRL.R |= 1 << i; /* Enable MB interrupt */
}

CAN_A.MCR.R = 0x0000003F; /* Negate FlexCAN C halt state for 64 MB */
}

Outcomes