LPC 1857 EMC Bus Timing & Static Parallel Flash

[jamestasker]

Hello,

I'm using the Keil MCB1800 development board (LPC1857) and am trying to use the NOR parallel flash for data storage. The flash chips are Spansion S29GL064N90TFI020 and there are two of them to for a 32-bit bus.  I'm using the Cypress/Spansion supplied low-level-driver to attempt to access the memory.  I'm running the EMC bus at 90 MHz and the processor at 180 MHz. 

The issue I'm seeing is that the commands that I send to the external flash, are not sent out on the EMC bus in the same order that they are designed to go out in code, or some commands are skipped all together (verified by scope).  I believe this may be because the processor is running much faster than the EMC and therefore the EMC cannot keep up with the data that it is supposed to send out??? If this is the case, what is the best practice and most efficient way to code up sequential commands (WR, RD, WR) or (WR, WR, WR, WR, WR, RD) to make sure they are being delivered or performed in the proper order?  I've tried waiting for the B and S bits in the EMC STATUS register to be clear before sending the next command, but this does not fix the issue.

Any thoughts or pseudo-code to help me get going would be fantastic.  Also, I'm new to using NOR static memory, so any good resources or example code of using/accessing external parallel flash in firmware would be appreciated (I couldn't find any examples that use/access the external parallel flash for the MCB1800).

Thanks in advance for your time.

-Jim

[jamestasker]

Thanks Jeremy and Bernhard for the input and feedback.  I've discovered that the reasoning for the out-of-order messages was due to the buffer being enabled for the static configuration register.  Once I disabled this buffer, the order was proper and everything began working properly.

In addition to the helpful .zip that Bernhard attached, I found the example code from Waveshare very useful (Core4357 - Waveshare Wiki ). 

Thanks again,

-Jim

[bernhardfink]

In Keil µVision there is a programming algorithm for this flash:

.\Keil_v5\ARM\Flash\S29GL064Nx2

I attached it as well.

I agree that the problem comes from the way the low-lvel driver writes onto the EMC, but for sure it is not a sync problem between the core and the EMC. These are synchronous designs, there is no cache or any sync bridge inbetween which could mix up the order of written instructions.

Maybe the EMC is not setup correctly in terms of data width, this 2 x 16-bit flash combination is tricky to handle.

Regards,

Bernhard.

[jeremyzhou]

Hi James Tasker，

Thank you for your interest in NXP Semiconductor products and 

the opportunity to serve you.

Unfortunately, there's no NOR Flash demo for the MCB1857 board, and I was wondering if you can share the initialization of NOR flash code, then I can check it for you.

TIC

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