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how to change run mode to HSRUN mode in s32k1xx

Question asked by sunju kim on Mar 27, 2018
Latest reply on Mar 28, 2018 by Diana Batrlova

hello everyone, I try to change the run mode of S32K144 with S32DS R1.2018

If someone has the HSRUN(SPLL 112MHz) mode setting then, I can analyze but anywhere I can't find that.

So I just try and make the HSRUN mode SPLL 112MHz but that is not working.

What is the problem? Could you help me? or Could you give me some information the way set HSRUN mode? or example?

 

My code is

 

void SCG_Init(void)

{

 // *** System OSC *** SOSC_CLK=8MHz

SCG->SOSCDIV=0x00000101;  /* SOSCDIV1 & SOSCDIV2 =1: divide by 1 */

SCG->SOSCCFG=0x00000034;  /* Range=3: high freq (SOSC betw 8MHz-32MHz)*/

                                                      /* HGO=0:   Config xtal osc for low power */

                                                      /* EREFS=1: Input is external XTAL */

while(SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK); /* Ensure SOSCCSR unlocked */

SCG->SOSCCSR=0x00000001;  /* LK=0:          SOSCCSR can be written */

 while(!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK));

while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */

SCG->SPLLCSR = 0x00000000;

while(!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */

 

// *** System FIRC ***

while(SCG->FIRCCSR & SCG_FIRCCSR_LK_MASK); /* Ensure FIRCCSR unlocked */

SCG->FIRCCSR = 0x00000000;   /* FIRCERR=0:   Fast IRC Clock Error */
                        /* FIRCSEL=0:   FIRC is not the system clock source */
                        /* FIRCVLD=0:   FIRC is not enabled or clock is not vaild */
                        /* LK=0:        FIRC can be written */
                        /* FIRCREGOFF=0:FIRC regulator is enabled */
                        /* FIRCEN =1 :  FIRC is Enable*/

SCG->FIRCDIV = 0x00000001; /* FIRCDIV1  = 1: divide by 1 */
SCG->FIRCCFG = 0x00000000;  /* Range=0:  (FIRC 48MHz)*/

 

SCG->FIRCCSR = 0x00000001;
  while(!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)); /* Wait for FIRC valid */

  SCG->RCCR=SCG_RCCR_SCS(3);
  SCG->HCCR=SCG_HCCR_SCS(3);

  SMC->PMPROT = 0x00000080; /*This line is make AHSRUN bit into 1 -> enabling high speed run*/
  SMC->PMCTRL = 0x00000060; //enter HSRUN

  // *** System PLL ***
  while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */
  SCG->SPLLCSR = 0x00000000;   /* LK=0:        SPLLCSR can be written */
                        /* SPLLCMRE=0:  SPLL CLK monitor IRQ if enabled */
                        /* SPLLCM=0:    SPLL CLK monitor disabled */
                        /* SPLLSTEN=0:  SPLL disabled in Stop modes */
                        /* SPLLEN=1:    Enable SPLL 일단 여기서 DISABLE?*/
  SCG->SPLLCFG = 0x000C0000;  /* PREDIV=0: Divide SOSC_CLK by 0+1=1 */
                               /* MULT=12:  Multiply sys pll by 12+16=28 */
                               /* SPLL_CLK = 8MHz / 1 * 28 / 2 = 112 MHz */
  SCG->SPLLDIV = 0x00000201;  /* SPLLDIV1 divide by 1 = 112MHz; SPLLDIV2 divide by 2 = 56MHz  */
  SCG->SPLLCSR = 0x00000001;
  while(!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */

  // *** MODE CONFIG ***  HSRUN 모드 Core_clk=112MHz, sys_clk = 112MHz, BUS_CLK=56MHz, FLASH_CLK=28MHz


  SCG->HCCR=SCG_HCCR_SCS(6)  /* PLL as clock source*/
     |SCG_HCCR_DIVCORE(0b00)  /* DIVCORE=0, div. by 1: Core clock = 112/1 MHz = 112 MHz*/
     |SCG_HCCR_DIVBUS(0b01)   /* DIVBUS=1, div. by 2: bus clock = 56 MHz*/
     |SCG_HCCR_DIVSLOW(0b11); /* DIVSLOW=3, div. by 4: SCG slow, flash clock= 28 MHz*/
  while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6) {}   /* Wait for sys clk src = SPLL */

  /* Write to PMPROT to allow VLLS3 power modes */

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