can imx6q support 4G DDR?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

can imx6q support 4G DDR?

3,389 Views
huiwang
Contributor II

can imx6q support 4G DDR?

Labels (1)
16 Replies

2,248 Views
igorpadykov
NXP Employee
NXP Employee

Hi hui

yes, one can create service request to obtain i.MX6Q schematic with 4GB support.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

2,248 Views
huiwang
Contributor II

Dear sir,

   we now use 32-bit Android, it also can support 4G DDR?

0 Kudos

2,248 Views
igorpadykov
NXP Employee
NXP Employee

yes it can.

Best regards
igor

0 Kudos

2,248 Views
huiwang
Contributor II

Dear dir,

   we now use only cs0 to connect four pcs DDR3(MT41K512M16 – 64 Meg x 16 x 8 banks),but only 2pcs(2G) is available.The method of  connecting of one DDR3 refers to the picture below.

The question is how can I change to support the whole 4G memory,to change the shematic or replace another DDR3 ??? 

Thanks a lot !

pastedImage_4.png

0 Kudos

2,248 Views
zhuyujun
Contributor II

Hello, hui wang:

   I have the same problem with you: use only cs0 to connect 4 DDR3(MT41K512M16 64Meg x 8 x 8banks x 2 die),

and I succeeded in DDR Test, but the Uboot can not run with DDR_MB=4096.

   However, if I set DDR_MB=3072 or DDR_MB=2048, it works successfully! Do you have solved problem?

   Look forward to your reply, thanks!

Best regards!

Yujun

0 Kudos

2,248 Views
j_zhang
Contributor II

Hi Yujun,

It sounds good that at least you succeed in DDR Test. Can you share your register programming values? Thank you very much!

Best regards,

Judy

0 Kudos

2,248 Views
zhuyujun
Contributor II

Hi Judy:

  This is my configuration for your reference:

pastedImage_1.png

Best regards!

Yujun

2,248 Views
eric_kang
Contributor II

Hi Yujun,
I'm using the same 4GB DDR3 in i.MX6Q and I'm using the just one CS, CS0.
And I have some problem.
When I executed some application, Display was broken during the first 1~2 seconds.

I don't know what's the problem.

Could you share your DDR configuration file?

and could you review our situation?

You can see the same problem in the below link.

https://community.nxp.com/message/1143889

Best Regards,

Eric.

0 Kudos

2,248 Views
twmemphis
Contributor III

Hi!

I would prefer to have the full file instead of just the basic settings.

As you set the tRCD/tRP/CL to 13.75ns, this - divided by cycle time of 1.894ns and rounded - results in 8 cycles for your CAS Latency and 7 cycles for CWL, which JEDEC calls a DDR3-1066 8-8-8 setting.

Per JEDEC the tRCmin at that speed and CL setting is 52.5ns and the tRAS min is 37.5ns

But I think the DDR Register Excel tool sometimes makes some wrong calculations, thus please send me the full file.

Usually tFAW is also set incorrectly.

And I have some questions, for example if you were running the calibration or not. And how did you find the DRAM DSE settings?

I have sent you a private message.

Regards,

Thorsten

0 Kudos

2,248 Views
twmemphis
Contributor III

Hi Yujun,

I am working with Junie on the issue and I think we are coming closer to get it solved. Some timings were incorrectly set, but still some fine tuning on the IOMUX SW PAD registers seems required as it still is not stable enough.

I would like to also help you as well to fix the timing registers. I have sent you a private message over this forum.

Regards,
Thorsten

0 Kudos

2,248 Views
zhuyujun
Contributor II

Hi, Thorsten:

  I have solved the problem, the max DDR size of i.MX6 is 3840MB:

pastedImage_1.png

  It works ok when I set DDR_MB=3840 in uboot.

Best regards!

Yujun

0 Kudos

2,248 Views
传策薛
Contributor V

Hi  hui wang:

一个cs0连接4片8Gb的DDR3是可行的吗?试验成功了吗?

0 Kudos

2,248 Views
j_zhang
Contributor II

Hi Everyone,

Did you make it work? I also built a board with four pieces of 8Gb DDR3 (IM8G16D3FCBG-125) and imx6q. It has always failed in stress test (memtester). I wonder what can we do in Register values to make it work. 

Has anyone tried Intelligent Memory 16Gb DD3? I am also very interested in knowing how it performs. 

Thank you! 

Judy

0 Kudos

2,248 Views
twmemphis
Contributor III

We have two customers running the 8Gb IM8G16D3FCBG on i.MX6 on their board. I will try to see if I can help you with a register dump from any of these two customers to verify where the issue is.

The 16Gb DDR3 is a future product from IM which is planned to be released in Q4

Regards,

Thorsten

0 Kudos

2,247 Views
igorpadykov
NXP Employee
NXP Employee

i.MX6Q MMDC (MMDCx_MDCTL) supports memories with max. RAW=16, COL=12

so you can try to find appropriate memory.

Best regards
igor

0 Kudos

2,247 Views
twmemphis
Contributor III

Such 8Gb DDR3L with 16 Row and 12 Column Addressing is available from Micron and Intelligent Memory

Micron MT41K512M16HA-125

Intelligent Memory IM8G16D3FCBG-125

Intelligent Memory also offers them with industrial temperature range of -40 to 95°C Tcase.

Out of curiosity: Would anybody know if it's possible to bring the i.MX6 to 8GB RAM by using 4GB per each chip select?

0 Kudos