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LPC11U68 Synchronous Mode USART0

Question asked by Nicholas Hunn on Mar 19, 2018
Latest reply on Mar 28, 2018 by Dezheng Tang

Hi, 

 

I'm having a weird problem with using the synchronous mode on the USART0 peripheral. 

 

I need to receive a bit stream sampled on the rising edge of a clock with no end or start bits, but attempting to set both of these parameters sets the sampling bit to falling. I can do rising with end and start or falling and no end and start but not both rising and no end and start. I can't even change it using the memory inspector in LPCXpresso.

 

For clarity, the syncctrl register  goes to 0x25 when I try to set it to 0x21.
This is the exact configuration I'm using

 

Chip_UART0_Init(LPC_USART0);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_UART0);
LPC_USART0->SYNCCTRL|=UART0_SYNCCTRL_SYNC|UART0_SYNCCTRL_STARTSTOPDISABLE; // Enable sync mode
Chip_UART0_SetupFIFOS(LPC_USART0,UART0_FCR_FIFO_EN); //Enable Input FIFO

Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 17,(IOCON_FUNC3 | IOCON_MODE_INACT));
Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 18,(IOCON_FUNC1 | IOCON_MODE_INACT));

 


How do I get around this issue, or is this some weird limitation of the chip?

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