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K66 NOR Flash Compatibility

Question asked by Jeremy Brookley on Mar 19, 2018
Latest reply on Mar 20, 2018 by Hui_Ma

Hello everyone!

 

This post ended up being longer than I expected so here's the TL;DR version:

 

1a)  Will Flexbus work with this chip (pinout on pg 9, read timing diagram on pg 12) ?

http://www.cypress.com/file/213346/download 

1b)  Would this be the correct wiring if this chip will work?

FLASHK66
CS#FB_CS0, FB_OE
CK#, CKFB_CLK
RWDSFB_RW
DQ[7:0]FB_D[7:0]

 

2a)  If it won't work with the chip in Q1, will it work with this chip (pinout on pg 8, read timing on pg 62) ?

http://www.cypress.com/file/202426/download 

2b)  Would this be the correct wiring if I'm using this chip?

FLASHK66
A[21:0]FB[21:0]
DQ[7:0]FB_D[7:0]
CE#FB_CS0
OE#FB_OE
WE#FB_R/W
WP#/ACC
ACC
WP#
RESET#
RY/BY#FB_BE/BWEn?
BYTE#

 

3)  For an application needing 64+ Mb of non-volatile RAM/Flash and wanting to minimize footprint, is there another RAM/Flash chip you'd recommend instead of the above suggestions?  L

 

Full post below (for those who want additional information/considerations):

 

I was originally looking at implementing NAND flash on a K60 but, due to changing specifications for this project, I'm transitioning to the K66 instead, which obviously doesn't support NAND flash.  It looks like I need 64+ Mb of non volatile flash and, based on what I'm reading, it sounds like our best bet is NOR Flash via the FlexBus lines.  To try and keep the footprint small, I'm looking at BGA based flash modules and came across Cypress' Hyperflash KL line.  One thing I'm not 100% sure of is if it will even be compatible (I'm guessing not as it doesn't appear to have address lines but instead communicates the address lines on the data lines).  Can anyone confirm or deny that it could work as intended on the FlexBus?  I know we can technically bitbang anything out but I'm trying to use the lines as intended without having to rewrite the code (which would obviously slowdown the communication rate). 


Below is the datasheet to the Hyperflash KL line (pinout on pg 9, read timing diagram on pg 12) :

http://www.cypress.com/file/213346/download 

 

If the above IS usable, I would assume I would hook it up as described below:

 

FLASHK66
CS#FB_CS0, FB_OE
CK#, CKFB_CLK
RWDSFB_RW
DQ[7:0]FB_D[7:0]

 

As I said above, I am fully anticipating this not working with the address being sent out on the data line but I thought I'd ask all the same. 

 

Failing that, we could actually use the GL-N line (or maybe a few others but these are the ones with the larger package sizes.  Below is a link to that datasheet (pinout on pg 8, read timing on pg 62):

http://www.cypress.com/file/202426/download 

 

Based on this, I assume the wiring for this chip would look like this:

FLASHK66
A[21:0]FB[21:0]
DQ[7:0]FB_D[7:0]
CE#FB_CS0
OE#FB_OE
WE#FB_R/W
WP#/ACC
ACC
WP#
RESET#
RY/BY#FB_BE/BWEn?
BYTE#

 

I tried to do as much research as I could before asking this question (hence it being probably longer than it needed to be so I added a TL;DR version above).  Any insight that can be provided when selecting a RAM/Flash chip based on our specifications would be appreciated.  If you think there's another chip that might better meet our needs, feel free to let me know. 

 

Thanks for all your help!

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