We are having issues with the link stability of Ethernet switch and PHY devices connected to the Serdes of processor P1022. Following is the used serdes configuration:-
cfg_serdes_ports : 10101
We are using both ethernet controllers in SGMII mode. We have two different assembly options for the card with only a slight difference in the processor schematic.Following are the observation for both options:-
Card 1: Both data path and control path(MIIM interface) for ETSEC 2 are working properly.
Card 2 : MIIM interface is not stable. Only like 10% of the times it reads correct values, otherwise random results are observed on the MDIO line. Data path is not working at all when link gets up at 1000 MBps, with 100 MBps speed link is up sometimes but it is also random.
There is no difference on the schematic of the PHY device used in both cards. In processor section following are the differences between card1 and card2 :
GPIO1_12 Pulled up via 10K resistor to 3.3 V
GPIO1_13 Floating connected to a level translator device
GPIO1_14 Pulled up via 10K resistor to 3.3 V
GPIO1_12 Pulled up via 10K resistor to 3.3 V and connected to a level translator device
GPIO1_13 connected to a level translator device
GPIO1_14 Pulled up via 10K resistor to 3.3 V and connected to a level translator device
GPIO1_15 connected to a level translator device
Attached is the relevant schematic section for your reference.
Note : In card 1 also this interface was not working earlier. Issue was resolved by replacing the bus-hold latch and buffer devices used at the local bus interface with the transparent latch and buffer devices.