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i.MX6 Solo & LPDDR2 Woes

Question asked by Jarrod Cook on Mar 16, 2018
Latest reply on May 4, 2018 by Jarrod Cook

So we designed a custom board with an i.MX6 Solo and LPDDR2 because we have an extremely weird and small form factor.  The first spin the LPDDR2 did not work and neither the calibration or speed tests would pass.  We cleaned up some circuit issues and redid the layout paying very close attention to trace length and impedance matching.  New board still doesn't work, not only that but they fail the same way as before.  It leads me to think we have some other problem going on here.

 

I am hoping someone has some suggestion for me as to what to try to narrow down this issue, because although I am going to keep scoping and playing with register settings to try and figure this out I really am at a loss as to what is going on.  Our LPDDR2 part is a Micron MT29RZ4B2DZZHHWD-18I.84F and i have attached our register settings file that we are using for the DDR Test Tool.  I have also attached the section of the schematic that has our RAM circuit.

 

Now what happens is the calibration will always fail in the DDR test tool, but if i run the stress test it will write 64-512 words before failing every time.  So to me that says wiring is correct because if i run it again it will write the byte it failed on without issue, but it will then fail again 64-512 words later : /.  Here is the output from DDR Test Tool to show you what i mean:

 

============================================
DDR Stress Test (2.6.0)
Build: Jan 24 2018, 14:20:57
NXP Semiconductors.
============================================

 

============================================
Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.3
============================================

 

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x32000001
============================================

ARM Clock set to 1GHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is LPDDR2 in 1-channel mode.
Data width: 32, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 256MB
Density per channel: 256MB
============================================

 

DDR Stress Test Iteration 1
Current Temperature: 76
============================================

DDR Freq: 396 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000040
Data was: 0xffffffff
But pattern should match address
Error: failed to run stress test!!!

 

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x1000003C: 0x1000003C 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
memory read is done

 

DDR Stress Test Iteration 1
Current Temperature: 76
============================================

DDR Freq: 396 MHz
t0.1: data is addr test
Address of failure(step2): 0x100000e0
Data was: 0xffffffff
But pattern should match address
Error: failed to run stress test!!!


0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x1000003C: 0x1000003C 0x10000040 0x10000044 0x10000048
memory read is done

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x100000DC: 0x100000DC 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
memory read is done

 

DDR Stress Test Iteration 1
Current Temperature: 77
============================================

DDR Freq: 396 MHz
t0.1: data is addr test
Address of failure(step2): 0x100001e0
Data was: 0xffffffff
But pattern should match address
Error: failed to run stress test!!!


0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x100000DC: 0x100000DC 0x100000E0 0x100000E4 0x100000E8
memory read is done

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x100001DC: 0x100001DC 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
memory read is done

 

Thanks for reading and hopefully someone has some suggestions for me as to where to go from here : /.

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