Could you confirm that the table 44-8 (MMDC refreshscheme) in IMX6DQRM.pdf) is actually correct? The text mentions that all configurations meet 3.9us refresh time... But to me it seems that 1 = 1,9us and 2 = 7,8us; An error in the document?
Additionally, could you elaborate on how option 1..4 "configure the desired AXI accesses delay/latency in each refresh cycle"? Why not always used the 4th?
Thanks in advance,