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DDR3 SDRAM ODT setting

Question asked by ko-hey on Mar 15, 2018
Latest reply on Mar 29, 2018 by Yuri Muhin

Hi all

 

Let me confirm about ODT setting of following signals. 

 

DRAM_ADDR[15:0]

DRAM_CAS

DRAM_CS0[1:0]

DRAM_DQM[7:0]

DRAM_ODT[1:0]

DRAM_RAS

DRAM_SDBA[2:0]

DRAM_SDCKE[1:0]

DRAM_SDCLK[1:0]_N

DRAM_SDCLK[1:0]_P

DRAM_SDWE

 

i.MX6 is output, but in the PAD setting register (IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, ...) of each of them, the 3 bits of the field 10: 8 are ODT setting.

 

(1) Since i.MX 6 side is output, so the ODT settings is disabled. Am I correct ?

(2)i.MX 6 is output but when ODT setting is set to Disable:
(2-1)

Is this setting effective?
In other words, is the terminating resistor actually connected inside the i.MX6 ?
(2-2)

If it is effective, if choosing an appropriate setting value will it help to improve the quality of the signal?

 

 

Ko-hey

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