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Streaming DDR3 contents via i.MX6 Dual

Question asked by Kevin Schilf on Mar 8, 2018
Latest reply on Mar 8, 2018 by igorpadykov

I have read several posts about connecting a FPGA via EMI or one of the video ports of the i.MX6 Dual, but I need to stream from DDR3 as quickly as possible (won't write to it).  In this application, the DDR3 will be loaded once and then will only be read from afterwards.  My initial plan is to DMA data out six ports to an FPGA which will re-assemble based on preset DMA transfer size.  I don't need any processing just straight from DDR3 to off-chip.  I am new to this product family.  Does this plan make sense?  How big is the transfer FIFO for each of these peripherals?

 

My initial plan from the IOMUX tool best case

 

IPU1_DI0_DISP_CLK

IPU1_DISP0_DATA[23:0]  ==> 150 MHz * 24 = 3.6 Gb

 

IPU1_DI1_DISP_CLK

IPU1_DISP1_DATA[23:0]  ==> 150 MHz * 24 = 3.6 Gb

 

LVDS0_CLK_N/P

LVDS0_DATA[3:0]_N/P ==> 85 MHz * 24 = 2.0 Gb

 

LVDS1_CLK_N/P

LVDS1_DATA[3:0]_N/P ==> 85 MHz * 24 = 2.0 Gb

 

SATA Phy (No "SATA" just raw bandwidth) ==> 2.4 Gb

 

PCIe Phy (FPGA has only a 3 Gb transceiver, No "PCIe" just raw bandwidth) ==> 2.0 Gb

 

Thank you for your assistance.

Kevin

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