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Bug with KL17? I2C Master producing glitches on SCL.

Question asked by Giorgos Karatziolas on Mar 7, 2018
Latest reply on Mar 9, 2018 by Giorgos Karatziolas

Bug Details 


We're using a MKL17Z64VLH4 microcontroller as a I2C master to communicate with a PMBus device. When left running, the microcontroller occasionally produces glitched clock edges as can be seen below.

I2C SDA glitch seen in place of 3rd clock pulse

The glitch can be seen here in place of the 3rd SCL pulse of the transmission. By counting the rest of the pulses, we can assume that when the master transmits this glitch, it believes that it is sending a full well-formed clock pulse. Data that we’ve collected shows that this glitch can occur in place of any of the clock pulses in the address transmission.


Is it possible that these glitches could be the result of misconfiguration of the I2C peripheral? Or has anyone seen similar glitches occurring? These glitches pose a fairly serious problem for us as some of them cause the I2C slaves to get confused and to hold the bus indefinitely (this can be seen at the end of the screenshot).




We’re making use of the HAL library in order to interface with the I2C peripheral.

The peripheral is configured with the following calls to:


// Enable main clock to I2C peripheral

SIM_HAL_EnableClock(SIM, kSimClockGateI2c1);

// Configure pins to run in I2C mode

PORT_HAL_SetMuxMode(I2C_SDA, kPortMuxAlt2);

PORT_HAL_SetMuxMode(I2C_SCL, kPortMuxAlt2);


// set baud rate to 100kHz

I2C_HAL_SetBaudRate(I2C1, i2cClockFreq, kI2cBaudRate, NULL);



Any help with this issue would be greatly appreciated!