On our system (a P2010 or P1014 configured in RC mode), we will occasionally get a machine check exception during reboot tests of startup initialization.
The machine check is marked as being a BUS_RBERR, and occurs on an lwz instruction to PCIe IO space.
- PEX_CONFIG_ADDR = 0x8001_0000 (EP's PCIe vendor ID read)
- PEX_CONFIG_DATA = 0x4c10_8888
- PEX_ERR_DR = 0x8002_0000
- bit 0 - multiple errors (this seems to always be on regularly during "good" operation)
- bit 14 - Access to an illegal configuration space from PEX_CONFIG_ADDR
- PEX_ERR_CAP_STAT = 0x0000_0041
- bit 25 - transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA
- bit 31 - error capture valid
What situations can cause the PCIe peripheral to generate this "Access to an illegal configuration space from PEX_CONFIG_ADDR"? Everything that we're doing seems valid and works 97% of the time. It's as if there is some sort of race condition that we're not aware of.
Huh, it looks like the LDD (Link down detected) bit is set in the PEX_PME_MES_DR register.
I think this would explain why access to the PCIe access would be considered illegal. Beyond some intermittent hardware issue, I can't think of a reason why this would occur.
Hello Seth Opgenorth,
The Link Down event is indicated in the PEXx_PEX_PME_MES_DR[LDD] and could be signaled by the corresponding interrupt, when PEXx_PEX_PME_MES_DISR[LDDD]=0 and PEXx_PEX_PME_MES_IER[LDDIE]=1.
In normal case it is needed to poll the PEX_LTSSM_STAT until the L0 state is reported. After reset or when recovering from a link down condition, external transactions should not to attempted until the link has successfully trained. Software can poll the LTSSM state status register (PEX_LTSSM_STAT) to check the status of link training before issuing external requests.
For details, please refer to LTSSM State Status Register(LTSSM_State_Status_Register) in the Reference Manual.
Have a great day,
TIC
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