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Can not config CLKOUT pin on DEVKIT-MPC5744P

Question asked by everk image on Mar 5, 2018
Latest reply on Mar 6, 2018 by everk image

I use example project Hello_World_PLL.

I Config PLL0 to 160MHz and use PLL0.PHI1 to support PLL1 to 200MHz.

Then make PLL1 support to SystemClock and CLKOUT pin output.

Finally i config the SIUL2.MSCR[PB6]=0x02000001,which means SSS=1(CLKOUT0),but SIUL2.MSCR[PB6] always get 0.

When i change to use PLL0 to support SystemClock,It's ok.

Is there something wrong?Please help.

 

Codes:
MC_CGM.AC3_SC.B.SELCTL = 1; //40 MHz XOSC selected as input of PLL0
PLLDIG.PLL0DV.B.RFDPHI1 = 8;
PLLDIG.PLL0DV.B.RFDPHI = 2;
PLLDIG.PLL0DV.B.PREDIV = 1;
PLLDIG.PLL0DV.B.MFD = 8;

 

MC_ME.DRUN_MC.R = 0x00130072;
MC_ME.MCTL.R = 0x30005AF0;
MC_ME.MCTL.R = 0x3000A50F;
while(MC_ME.GS.B.S_MTRANS == 1); /* Wait for mode transition complete */

 

MC_CGM.AC4_SC.B.SELCTL=0b11; //PLL0_PHI1 selected as input of PHI1
PLLDIG.PLL1DV.B.RFDPHI = 2;
PLLDIG.PLL1DV.B.MFD = 20;
PLLDIG.PLL1FD.B.FRCDIV = 0;

MC_ME.DRUN_MC.R = 0x001300F4;   //If i change this to 0x001300F2,it's ok.
MC_ME.MCTL.R = 0x30005AF0;
MC_ME.MCTL.R = 0x3000A50F;
while(MC_ME.GS.B.S_MTRANS == 1); /* Wait for mode transition complete */


/* Set Up clock selectors to allow clock out 0 to be viewed */
MC_CGM.AC6_SC.B.SELCTL = 4; /* Select PLL1 (PLL1-sysclk0) */
MC_CGM.AC6_DC0.B.DE = 1; /* Enable AC6 divider 0 (SYSCLK0)*/
MC_CGM.AC6_DC0.B.DIV = 9; /* Divide by 10 */

/* Configure Pin for Clock out 0 on PB6 */
SIUL2.MSCR[PB6].R = 0x02000001; /* PB6 = 22 SRC=2 (Full drive w/o slew) SSS=1 (CLKOUT_0) */

 

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