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s32k can1 is not work

Question asked by xu zeze on Mar 5, 2018
Latest reply on Mar 14, 2018 by Petr Stancik

S32K can1 not work ,can0 is ok.My mcu is s32k144-64pins . The following is my code :

 

void FlexCAN_init_IRQs(void) {
//can0
    FSL_NVIC->ICPR[2] = 1 << (CAN0_ORed_0_15_MB_IRQn % 32); /*  ch0: clr any pending IRQ*/
    FSL_NVIC->ISER[2] = 1 << (CAN0_ORed_0_15_MB_IRQn % 32); /*  ch0: enable IRQ */
    FSL_NVIC->IP[CAN0_ORed_0_15_MB_IRQn] = 0xA;             /*  ch0: priority 10 of 0-15*/
//can1
    FSL_NVIC->ICPR[2] = 1 << (CAN1_ORed_0_15_MB_IRQn % 32); /*  ch0: clr any pending IRQ*/
    FSL_NVIC->ISER[2] = 1 << (CAN1_ORed_0_15_MB_IRQn % 32); /*  ch0: enable IRQ */
    FSL_NVIC->IP[CAN1_ORed_0_15_MB_IRQn] = 0xA;             /*  ch0: priority 10 of 0-15*/

}

 

void CAN1_ORed_0_15_MB_IRQHandler() {
    /* Read message */

    FLEXCAN1_receive_msg();
}

 

void FlexCAN_PORT_init(void) {

    PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK;
    PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
    PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; /* Enable clock for PORTE */
    //CAN 0
    PORTC->PCR[2] |= PORT_PCR_MUX(3); /*  CAN0_RX */
    PORTC->PCR[3] |= PORT_PCR_MUX(3); /*  CAN0_TX */
    PORTD->PCR[7] |= PORT_PCR_MUX(1); /*  CAN0_STAND*/
    //CAN 1
    PORTC->PCR[6] |= PORT_PCR_MUX(3); /*  CAN1_RX */
    PORTC->PCR[7] |= PORT_PCR_MUX(3); /*  CAN1_TX */
    PORTE->PCR[6] |= PORT_PCR_MUX(1); /*  CAN1_STAND*/
    //can2
    PORTC->PCR[16]|= PORT_PCR_MUX(3); /*  CAN2_RX */
    PORTC->PCR[17]|= PORT_PCR_MUX(3); /*  CAN2_TX */

    PTD->PDDR |= 1 << 7;
    PTE->PDDR |= 1 << 6;
    PTD->PCOR |= 1 << 7;
    PTE->PCOR |= 1 << 6;
//  can mode sel
    CAN0_NORMAL();
    CAN1_NORMAL();
}

 

void FLEXCAN0_init(uint32_t speed_value) {

    uint32_t i = 0;

    PCC->PCCn[PCC_FlexCAN0_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */
    CAN0->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
    CAN0->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = oscillator (8 MHz) */
    CAN0->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/
    while (!((CAN0->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {
    }
    CAN0->CTRL1 = speed_value;
    for (i = 0; i < 64; i++) { /* CAN0: clear 32 msg bufs x 4 words/msg buf = 128 words*/
        CAN0->RAMn[i] = 0; /* Clear msg buf word */
    }
    for (i = 0; i < 16; i++) { /* In FRZ mode, init CAN0 16 msg buf filters */
        /*Configure based on need*/
        CAN0->RXIMR[i] = 0; /* Check all ID bits for incoming messages */
    }
    CAN0->RXMGMASK = 0; /* Global acceptance mask: check all ID bits */
    /*Change the masking based on MLC adress*/
    CAN0->RAMn[4 * MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */

    CAN0->RAMn[4 * MSG_BUF_SIZE + 1] = 0x14440000; /* Msg Buf 4, word 1: Standard ID = 0x111 */
    CAN0->RAMn[2 * MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */

    CAN0->RAMn[2 * MSG_BUF_SIZE + 1] = 0x14440000; /* Msg Buf 4, word 1: Standard ID = 0x111 */
    CAN0->RAMn[3 * MSG_BUF_SIZE + 0] = 0x04000000; /* Msg Buf 4, word 0: Enable for reception */
    CAN0->RAMn[3 * MSG_BUF_SIZE + 1] = 0x14440000; /* Msg Buf 4, word 1: Standard ID = 0x111 */

 

    /* PRIO = 0: CANFD not used */
    CAN0->MCR = 0x0002001F; /* Negate FlexCAN 1 halt state for 32 MBs */
    CAN0->IMASK1 = 0x0000001C;
    while ((CAN0->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {
    }
    /* Good practice: wait for FRZACK to clear (not in freeze mode) */
    while ((CAN0->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {
    }
    /* Good practice: wait for NOTRDY to clear (module ready)*/
}

 

void FLEXCAN1_init(uint32_t speed_value) {
    uint32_t i = 0;

    PCC->PCCn[PCC_FlexCAN1_INDEX] |= PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN1 */
    PCC->PCCn[PCC_FlexCAN1_INDEX] = PCC_PCCn_CGC_MASK; /* CGC=1: enable clock to FlexCAN0 */


    CAN1->MCR |= CAN_MCR_MDIS_MASK; /* MDIS=1: Disable module before selecting clock */
    CAN1->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; /* CLKSRC=0: Clock Source = oscillator (8 MHz) */
    CAN1->MCR &= ~CAN_MCR_MDIS_MASK; /* MDIS=0; Enable module config. (Sets FRZ, HALT)*/

 

    while (!((CAN1->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT)) {
    }
    CAN1->CTRL1 = speed_value;
    for (i = 0; i < 64; i++) { /* CAN1: clear 16 msg bufs x 4 words/msg buf = 64 words*/
        CAN1->RAMn[i] = 0; /* Clear msg buf word */
    }
    for (i = 0; i < 16; i++) { /* In FRZ mode, init CAN1 16 msg buf filters */
        CAN1->RXIMR[i] = 0; /* Check all ID bits for incoming messages */
    }

    CAN1->MCR = 0x0002000f; /* Negate FlexCAN 1 halt state for 16 MBs */
    CAN1->IMASK1 = 0x0000000f;

    while ((CAN1->MCR && CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) {
    }
    /* Good practice: wait for FRZACK to clear (not in freeze mode) */
    while ((CAN1->MCR && CAN_MCR_NOTRDY_MASK) >> CAN_MCR_NOTRDY_SHIFT) {
    }
    /* Good practice: wait for NOTRDY to clear (module ready)*/
}

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