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LPC4370 getting max 80MHz rate

Question asked by ravi thakur on Mar 5, 2018
Latest reply on Mar 26, 2018 by jeremyzhou

I have the LPC-link2 that I am using as a development board and using HSADC0. I am using USB0 PLL to generate the 80MHz sampling rate and the base clocks are running at 204MHz. When programming the descriptor tables, I am setting the match value to to '1'. I intend to capture data at 80MHz. It seems like the match value of '1' divides the 80MHz clock by 2. I do not see any overflow interrupts. Setting the match value to '0' causes a descriptor error interrupt as soon as I enable the HSADC interrupts without even updating the descriptor table. My code snippet is pasted below. The match value is set to '1' in it. When I set the value to '0', as soon as the execution comes to the line

"NVIC_EnableIRQ(ADCHS_IRQn)", it goes in to the ADC interrupt handler next. Please advise.

 

static void initHSADC() {

// Setup FIFO trip points for interrupt/DMA to 8 samples, packing
Chip_HSADC_SetupFIFO(LPC_ADCHS, 8, true);

 

// Software trigger only, 0x90 recovery clocks, do not add channel Info to FIFO entry
Chip_HSADC_ConfigureTrigger(LPC_ADCHS, HSADC_CONFIG_TRIGGER_SW,
HSADC_CONFIG_TRIGGER_RISEEXT, HSADC_CONFIG_TRIGGER_NOEXTSYNC,
HSADC_CHANNEL_ID_EN_NONE, 0x90);

 

// Enable negative pin bias and disable ADCHS 0 bias
Chip_HSADC_SetACDCBias(LPC_ADCHS, 0, HSADC_CHANNEL_DCBIAS,
HSADC_CHANNEL_NODCBIAS);

 

// Setup data format for 2's complement and set power and speed values for the set fADC
Chip_HSADC_SetPowerSpeed(LPC_ADCHS, true);

 

// Enable HSADC power
Chip_HSADC_EnablePower(LPC_ADCHS);

 

// table 0 : mapped to input 0, match time to 1, reset timer, branch to next descriptor, no threshold detection
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 0, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_NEXT |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 1, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_NEXT |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 2, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_NEXT |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 3, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_NEXT |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 4, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_NEXT |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 5, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_NEXT |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 6, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_NEXT |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 7, (HSADC_DESC_CH(0) | HSADC_DESC_BRANCH_FIRST |
HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));

 

// Setup HSADC interrupts on group 0 - FIFO trip (full), FIFO overrun error, and descriptor status error
Chip_HSADC_EnableInts(LPC_ADCHS, 0, (HSADC_INT0_FIFO_FULL | HSADC_INT0_DSCR_ERROR | HSADC_INT0_FIFO_OVERFLOW));

 

// Enable HSADC interrupts in NVIC
NVIC_DisableIRQ(ADCHS_IRQn);
NVIC_SetPriority(ADCHS_IRQn, 0x2);
NVIC_EnableIRQ(ADCHS_IRQn);

 

// Update descriptor tables
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 0);
}

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