AnsweredAssumed Answered

Boot the DSP multiple times without using target reset.

Question asked by Ahmad Nour on Mar 4, 2018
Latest reply on Mar 7, 2018 by Ahmad Nour

Hello,

 

Is there anyway to be able to re-run the program multiple times (on the DSP) without using 'tgreset' command?

 

On the first trial, 'dsp boot' dumps the following output:

 

Het Mgr 248 0
IPC: dsp_shared_size - 0x1000000
IPC: dsp_private_addr - 0x80000000
IPC: dsp_private_size - 0x7ff00000
IPC: shared_ctrl_addr - 0xfff00000
IPC: shared_ctrl_size - 0x100000
IPC: max_num_ipc_channels  64
IPC: max_channel_depth  16
fsl_shm module installed successfully withmajor num : 247
fsl_l1d Major=246 Minor=0
===B4860QDS DSP boot Application (3.0.0) ===
SYSTEM MAP
DSP PrivArea: Addr=80000000 Size=7ff00000
Shared CtrlArea: Addr=fff00000 Size=100000
DSP Core0 M2: Addr=0 Size=0
DSP Core1 M2: Addr=0 Size=0
DSP M3: Addr=c40000000 Size=8000
PA CCSRBAR: Addr =ffe000000 Size=1000000
DSP CCSRBAR: Addr =ffe000000 Size=1000000
DBG: Addr =0 Size=0
PA Shared Area: Addr=60000000 Size=f000000
DSP Shared Area: Addr=6f000000 Size=1000000
PA Debug Print Shared Area: Addr=0 Size=0
DSP Debug Print Shared Area: Addr=c40000000 Size=8000
Loading Dsp image eNBL1.bin

 Copy Part 80000000 2c1bc

 (repeated copying commands)
 Copy Part a40b4000 32c42
intvec_addr =a405e000 in L1 Binary
Before StarCore release ========
LCC_BSTRH=0x0
LCC_BSTRL=0x7ffff000
LCC_BSTAR=0x8110000b
GCR_CDCER0=0x0
GCR_CHMER0=0x0
DCFG_BRR=0xf
 After StarCore release ========
LCC_BSTRH=0x0
LCC_BSTRL=0xa405e000
LCC_BSTAR=0x8100000c
GCR_CDCER0=0x3f0
GCR_CHMER0=0x3f00
DCFG_BRR=0x3ff
BSTRL,BSTAR,CDCERO,CHMERO n DCFG_BRR set now
sleep 1, waiting for hw sem
sleep 1, waiting for hw sem
HS_MPR[1]=0xfe
HS_MPR[1]=0x0


 == DSP Booted up ==

 

The next time I run 'dsp boot' without 'tgreset', I get the following output:

 

Het Mgr 248 0
IPC: dsp_shared_size - 0x1000000
IPC: dsp_private_addr - 0x80000000
IPC: dsp_private_size - 0x7ff00000
IPC: shared_ctrl_addr - 0xfff00000
IPC: shared_ctrl_size - 0x100000
IPC: max_num_ipc_channels  64
IPC: max_channel_depth  16
fsl_shm module installed successfully withmajor num : 247
fsl_l1d Major=246 Minor=0
===B4860QDS DSP boot Application (3.0.0) ===
SYSTEM MAP
DSP PrivArea: Addr=80000000 Size=7ff00000
Shared CtrlArea: Addr=fff00000 Size=100000
DSP Core0 M2: Addr=0 Size=0
DSP Core1 M2: Addr=0 Size=0
DSP M3: Addr=c40000000 Size=8000
PA CCSRBAR: Addr =ffe000000 Size=1000000
DSP CCSRBAR: Addr =ffe000000 Size=1000000
DBG: Addr =0 Size=0
PA Shared Area: Addr=60000000 Size=f000000
DSP Shared Area: Addr=6f000000 Size=1000000
PA Debug Print Shared Area: Addr=0 Size=0
DSP Debug Print Shared Area: Addr=c40000000 Size=8000
Loading Dsp image eNBL1.bin

 Copy Part 80000000 2c1bc
 (repeated copying commands)
 Copy Part a40b4000 32c42
intvec_addr =a405e000 in L1 Binary
Before StarCore release ========
LCC_BSTRH=0x0
LCC_BSTRL=0xa405e000
LCC_BSTAR=0x8100000c
GCR_CDCER0=0x3f0
GCR_CHMER0=0x3f00
DCFG_BRR=0x3ff
 After StarCore release ========
LCC_BSTRH=0x0
LCC_BSTRL=0xa405e000
LCC_BSTAR=0x8100000c
GCR_CDCER0=0x3f0
GCR_CHMER0=0x3f00
DCFG_BRR=0x3ff
BSTRL,BSTAR,CDCERO,CHMERO n DCFG_BRR set now

sleep 1, waiting for hw sem
sleep 1, waiting for hw sem

Infinitely repeated (sleep 1, waiting for hw sem)

Am I missing something?

Is there a way to reset the DSP without using 'tgreset'?

 

Thanks,

Outcomes