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PCIe Inbound Window Configuration on P1011

Question asked by Eric Fornstedt on Mar 1, 2018
Latest reply on Mar 15, 2018 by Eric Fornstedt

Hi,

 

We have a working PCIe configuration between out P1011 CPU and an FPGA, where P1011 is the Root Complex and FPGA is the Endpoint. One outbound window is defined and working properly when P1011 is the initiator. But, we are having a problem with the inbound window. A detailed description of relevant registers for the working outbound configuration looks like this:

 

PEX1_PEXOTAR10x000A0000Translation address 0xA0000000
PEX1_PEXOWBAR10x000A0000Base Address 0xA0000000
PEX1_PEXOWAR10x80044012Enable, Default order, Snoopable, TC0, Mem Read, Mem write, 512 kB Size

 

LAW_LAWBAR00x000A0000 Local Access Window 0xA0000000
LAW_LAWAR00x8020001C Enable, Target PEX1, 512 MB Size
L2MMU_CAM120xA0007FCA1C0800008000000080000001A window at 0x80000000 of size 1 GB

  

Bus 0, Device 0, Fuction 0 - Configuration space 
0x040x00100106Command Status: Capabilities List - Command Register: SERR, Bus Master, Memory Space
0x080x0B200011Class Code: Processor, PowerPC, RC mode. Revision: 0x11
0x100xFFF00000PEXCSRBAR: The fixed 1 MB window
0x180x00010100Sec latency: 0, Subordinate bus: 1, Secondary bus 1, Primary bus 0

 

Bus 1, Device 0, Fuction 0 - Configuration space 
0x040x00100106Command Status: Capabilities List - Command Register: SERR, Bus Master, Memory Space
0x100xA0000000Base address 0xA00000000

 

As far as we can see this works fine. Our problem starts when we try to define an inbound window to enable the FPGA to be initiator of messages to read/write directly into the DDR memory connected to P1011. The approach we have tried looks like this:

 

PEX1_PEXITAR10x00000030Let Endpoint read from address 0x00003000 (DDR). There is also a TBL entry for 0x00003000 of size 16 MB.
PEX1_PEXIWBAR10x000A0000Base address 0xA0000000 (we have also tried 0x00000000)
PEX1_PEXIWAR10xA0F4401BEnable, Prefetchable, Local Mem Space, 1 MB Size

 

Bus 0, Device 0, Fuction 0 - Configuration space additions 
0x240xC0010001Prefetchable base 0x00000000, limit 0xC0000000, type 64-bit (also tried with default limit 0x00000000)

 

What happens is that P1011 receives a memory read request which seems valid according to what we can see, but for some reason it is not accepted and an "Unsupported Request" error is raised.

 

Bus 0, Device 0, Fuction 0 - Configuration space
0x11C0x00000001PCI Express Header Log Reg 1: Mem read request from Endpoint
0x1200x0100000FPCI Express Header Log Reg 2: Requester 0x0100 (bus 1, device 0, function 0), 1st BE 0xF
0x1240x000E0000PCI Express Header Log Reg 3: Address requested from Endpoint
0x040x40100106Command Status: Signaled System Error, Capabilities List - Command Register: SERR, Bus Master, Memory Space
0x1040x00100000Uncorrectable Error Status Register: Unsupported request error
0x1180x000000B4PCIe Advanced Error Capabilities and Ctrl Reg: First_Error_Pointer: 0x14, ECRC generation capable: 1, ECRC checking capable: 1
0x1300x0000002CRoot Error Status Register: NFEMR, MEFNFR, EFNFR

 

Bus 1, Device 0, Fuction 0 - Configuration space
0x040x20100106Command Status: Received Master Abort, Capabilities List - Command Register: SERR, Bus Master, Memory Space

 

We have tried to investigate why this happens without success and would appreciate any help to guide us where to dig further.

 

BR
/ Eric

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