According to our requirement the interface through SFP+ connector should work either for 10/1G.
What is the restriction from processor side for 1G and 10G INTERFACE on XFI1(lane B).
Our doubt is that whether a PHY is required to handle this or can it be taken care by the processor.
As per our understanding for XFI at 10G operation SRDS_PRTCL_S2 value=39H as per table 8 of reference manual, whether same lane can be configured for SGMII by changing the value of SRDS_PRTCL_S2 to 23H.
Is there any electrical characteristics difference between XFI and SGMII when configured on the same SERDES lane as per end application either 1G or 10G?
If clock requirement is only the concern, it can be taken care through configurable clock synthesizer which can generate either 156MHz LVDS or 100MHz HCSL for processor reference clock.
If processor can be configured for 10/1G then alone retimer can meet the requirement, else we may have to use PHY. We are planning to use 10G retimer DS110DF11 from TI. As per our understanding this supports both 10/1G.
Will buffer overflow happen if there is any mismatch between processor and PHY/Retimer?