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SMP Cache Coherency on i.MX6

Question asked by Jonathan Ankers on Feb 27, 2018
Latest reply on Feb 27, 2018 by Yuri Muhin



I've been having problems with the cache coherency on the i.MX6 SABRE Lite.


As I understand it, providing that I set up the MMU/caches/SCU/SMP bit correctly, I should not have to perform any explicit cache operations in order for the cached memory to be kept coherent between multiple cores.


I writing a custom bootloader, and the issue that I'm having is that sometimes when I power the board (at least once in every 10 runs), the cache coherency seems to not be working properly, but other times it appears to be working fine. In the cases where it is not working, I can attach a debugger and see that the memory is not coherent between the cores.


My boot sequence is as follows (in pseudocode) -


if (core 0) [invalidate whole SCU; Enable SCU]
disable dcache
disable icache

disable mmu
enable SMP (including setting ACTLR.FW bit)
invalidate TLB
invalidate dcache
invalidate icache
enable mmu
enable dcache
enable icache
if (core 0) [GOTO core0_specific]
else [GOTO coreN_specific]

invalidate l2cache
enable l2cache
start cores 1..N at address boot_entry_point
branch to main

branch to main


For the coherent memory areas, I have the MMU Map setup as Shared, Inner and Outer Write Back Write Allocate.


I have also implemented any relevant Errata from the i.MX6 Dual/Quad Chip Errata (e.g. ERR004325), though I believe that the coherency doesn't work too often for it to be down to a chip Errata.


I have a Zynq 7000 board (ARM A9 Dual Core) running very similar code that does not show any problems. Is there any reason why the cache coherency would not work as I expect on the i.MX6 SABRE Lite?