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Problem enabling ECSPI on iMX6ULL

Question asked by Jesper Lindgren on Feb 26, 2018
Latest reply on Feb 28, 2018 by Jesper Lindgren

Hello,

 

We have a custom board based on the iMX6ull processor that we try to enable ECSPI4 on. Below you find the board dts file with the added ECSPI declarations. The problem we run into is that during kernel boot, when initializing the spi-imx driver executing stops suddenly. We have traced this to the method call mx51_ecspi_reset() in spi-imx.c. Eveything stops when the readl(spi_imx->base + MXC_CSPIRXDATA) line is executed. Further debugging shows that execution stops as soon as either a readl or a writel call is performed. We are building using the linux-imx repository and use the branch imx_4.1.15_2.0.0_ga

 

1. Can you see what we might have done wrong?

2. Are we using the correct branch? Is there a newer branch that is more recently supported for the iMX6ull?

3. Have we configured the iomux correctly for the ecspi? Is there a reference as to what the 0x100b1 parameter means on the ecspi iomux lines? (We've taken them from other topics on these forums)

 

Thankful for any help we can get.

 

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx6ull.dtsi"

/ {
     model = "Custom board";
     compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";

     chosen {
          stdout-path = &uart1;
     };

     memory {
          reg = <0x80000000 0x08000000>;
     };

     reserved-memory {
          #address-cells = <1>;
          #size-cells = <1>;
          ranges;

          linux,cma {
               compatible = "shared-dma-pool";
               reusable;
               size = <0x14000000>;
               linux,cma-default;
          };
     };

     spi3 {
          status = "okay";
     };
};


&fec1 {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_enet1>;
     phy-mode = "rmii";
     phy-handle = <&ethphy0>;
     status = "okay";

     mdio {
          #address-cells = <1>;
          #size-cells = <0>;

          ethphy0: ethernet-phy@2 {
               compatible = "ethernet-phy-ieee802.3-c22";
               reg = <2>;
          };
     };
};

&fec2 {
     status = "disabled";
};

&iomuxc {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_hog_1>;
     imx6ul-evk {
          pinctrl_hog_1: hoggrp-1 {
               fsl,pins = <
                    MX6UL_PAD_UART1_RTS_B__GPIO1_IO19     0x17059 /* SD1 CD */
                    MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT     0x17059 /* SD1 VSELECT */
                    MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
               >;
          };

          pinctrl_enet1: enet1grp {
               fsl,pins = <
                    MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN     0x1b0b0
                    MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER     0x1b0b0
                    MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00     0x1b0b0
                    MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01     0x1b0b0
                    MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN     0x1b0b0
                    MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00     0x1b0b0
                    MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01     0x1b0b0
                    MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1     0x4001b031
                    MX6UL_PAD_GPIO1_IO06__ENET1_MDIO     0x1b0b0
                    MX6UL_PAD_GPIO1_IO07__ENET1_MDC          0x1b0b0
               >;
          };

          pinctrl_qspi: qspigrp {
               fsl,pins = <
                    MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
                    MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
                    MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
                    MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
                    MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
                    MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
               >;
          };

          pinctrl_ecspi4: ecspi4grp {
               fsl,pins = <
                    MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1
                    MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1
                    MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1
               >;
          };

          pinctrl_ecspi_cs0: ecspi_cs0 {
               fsl,pins = <
                    MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0
               >;
          };

          pinctrl_uart1: uart1grp {
               fsl,pins = <
                    MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
                    MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
               >;
          };

          pinctrl_uart2: uart2grp {
               fsl,pins = <
                    MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX     0x1b0b1
                    MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX     0x1b0b1
               >;
          };

          pinctrl_wdog: wdoggrp {
               fsl,pins = <
                    MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
               >;
          };
     };
};

&qspi {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_qspi>;
     status = "okay";
     ddrsmp = <0>;

     flash0: s25fl256sl@0 {
          #address-cells = <1>;
          #size-cells = <1>;
          compatible = "spansion,s25fl256s1";
          spi-max-frequency = <29000000>;
          spi-nor,ddr-quad-read-dummy = <6>;
          reg = <0>;
     };
};

&ecspi4 {
     fsl,spi-num-chipselects = <1>;
     cs-gpio = <&gpio2 15 0>; /* GPIO3_24 */
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_ecspi_cs0>;
     status = "okay";

     spidev@0x00 {
          compatible = "spidev";
          reg = <0>;
          spi-max-frequency = <80000000>;
     };
};

&uart1 {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_uart1>;
     status = "okay";
};

&uart2 {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_uart2>;
     status = "okay";
};

&wdog1 {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_wdog>;
     fsl,wdog_b;
};

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