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Flush L1 cache on MPC5777M?

Question asked by jschloss on Feb 26, 2018
Latest reply on Mar 1, 2018 by David Tosenovjan

Looking at ch 15.7.91 in the MPC5777M reference manual, I see I can invalidate the data cache by set and way using L1FINV0, but there is not a cache command that lists flush, just invalidate. Can this register flush the cache, or do I have to use dcbf (potentially over all of cache-able memory?) to flush the cache? Also, if I set the L1CSR0.DCWA bit to zero, will all writes be noncache-able?