I'm trouble in interfacing between FEC and TJA1100 phy.
my test environment is:
- linux 4.9.11
- MII mode ( 4bits data, 100M duplex, 25MHz txc/rxc as separate clock)
with current driver, receive part is working well from PC to RAD Moon(Signal converter) to target board.
when PC side sends ping command to target board, it responds to ping command properly by checking data with tcpdump tool. and target board side shows ping reply response correctly, but actual transmission failed to reply ping for PC side. that's why transmission data is not working well from FEC to Phy.
I've captured some waveforms by using CRO.
FEC test environment is:
- tx data: data 10 alternate , for example, 10100101( 0x5a)
- digital loopback(PCS block) in TJA1100
- txd pin, rxd pin captured by CRO
if data can be generated 1010 alternate at FEC side, drivers/net/ethernet/freescale/fec_main.c, I could see data at each TXD0,1,2,3.
as you see, tx data seems to be fed into phy without problem, but the resultant digital loopback data are shown some 1s string and other 0s except single normal output.
[FEC TX data from imx6ull ]
[RX data from phy after digital loopback]
and I've tried to narrow down this problem in terms of tx data and tx clock.
data is clocked on rising edge for 10M/100Mbps. strangely, data 10 alternate was generated on rising and falling edge synchronous. I've tried to look at reference manual and fec_main.c, failed to fix it except FEC_QUIRK_HAS_GBIT at fec_main.c. that's why 1GBS data is clocke on both(falling/rising)edge synchronously.
here's the problematic waveform by CRO
- yellow line: tx clock
- green line: tx data
[all 1's data captured at Phy side, though tx data 10 alternate transmitted at FEC side]
[all 0's data captured at Phy side, though tx data 10 alternate transmitted at FEC side]
do you have patch driver for fixing it up?
please, refer to current fec driver as attached( linux4.9.11 )
Thanks in advance.