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The Questions related to Power Up/Down Sequencing of MPC5125

Question asked by SANG-RAE LEE on Feb 23, 2018

Dear All.

My name is SANG-RAE LEE who is hardware engineer worked for IT-Telecom in Korea. 

Main items of our company are V2X products and main chipsets are i.MX6 and MPC5125 of NXP.

Now, there is a problem with our product including MPC5125.

Please, refer to below for more information.

 

   1) CPU : MPC5125

   2) PROBLEM

        (1) The status of all power supply is OK.

        (2) The status of all clock signal is OK.

        (3) But, our product is not operated in some cases(booting failure), even if that is booting up in some cases.

    3) OUR FAILURE ANALYSIS

        (1) We have not found any reasons to solve this problem.

        (2) So, we have checked power up/down sequencing of MPC5125.

    4) OUR REFERENCE DOCUMENT

        (1) DOCUMENT NUMBER : MPC5125 Rev. 4, 09/2011(MPC5125 Microcontroller Data Sheet)

        (2) Please, refer to below for our asking contents in page 83 of datasheet.

 

<The contents of datasheet>

===========================================================================================

5 System Design Information
     5.1Power Up/Down Sequencing
         Power sequencing between the 1.4 V power supply VDD and the remaining supplies is required to prevent       excessive current during power-up phase.


        The required power sequence is as follows:
               • Use 12 V/ms or slower time for all supplies.
               • Power up VDD_IO, AVDD_PLLs, VBAT (if not applied permanently), and VDD_IO_MEM supplies first in any order, and then power up VDD. If required AVDD_FUSEWR should be powered up afterwards.
               • All the supplies must reach the specified operating conditions before the PORESET can be released.
               • For power down, drop AVDD_FUSEWR to 0 V first, drop VDD to 0 V, and then drop all other supplies.
               • VDD should not exceed VDD_IO, VDD_IO_MEM, VBAT, or AVDD_PLLs by more than 0.4 V at any time, including power-up.

===========================================================================================

 

    5) OUR QUESTIONS

        (1) Can you explain 12 V/ms ?  We can not understand mean of 12 V/ms.

        (2) Is power up sequencing mantatory requirement? (VDD_IO > VDD)

              The power up sequencing of our product is different with datasheet.

              There is no difference in power up time between VDD_IO and VDD  in our product

              Is there any possible to make trouble in power up sequencing due to no difference in power up sequencing?

        (3) Is power down sequencing mantatory requirement? (VDD > VDD_IO)

             What are predictable problems if this requirement is not satisfied?

 

 

Please, help us to solve this problem.

 

Thank you.

Good Bye.

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