I have a custom T4080 design that I have been using the BDI3000 to run U-boot from SRAM. The T4080 gets its RCW and PBI from an I2C eeprom. I have a NOR flash on IFC Chip Select 0 which I want to boot U-boot from. When I disconnect the BDI and let the processor boot normally I never see any Chip Selects on CS0 which is the BOOT_LOC in the RCW. I know that it gets all the way down the Reset and Initialization sequence to run PBI because I can see our IFC bus go from 50MHZ to 100MHZ which is set by the clock divider in the PBI. That leads me to believe we are getting to step 18 System Ready State. Unfortunately, I do not have the ASLEEP signal pulled over to our FPGA which pulls in all the other JTAG signals, so I cannot verify that portion. HRESET_B seems to be high and HRESET_REG_B does not seem to be low.
Does anyone have a suggestion on if I can still hook up the BDI and have it run the normal reset sequence of the T4080 instead of halting it, or any other signals I should be looking at?
Can the T4080 go to an Interrupt vector before the boot vector?