I am using an LPC1549 in an IOT application and I had some issues with power consumption. After a week-long investigation, I found something very odd and wondered if anyone else had come across this or if NXP would like to comment...
My application doesn't use USB so I left the D+/D- pins unconnected. I found that touching the pins dramatically changes the power consumption in power down mode. Table 34 of the datasheet says that if the USB PHY is off, the pins are LOW. However, applying an external pull-up actually reduces the chip power consumption. So I concluded that the pins are not driven when the PHY is off. Turning on the 1k5 internal pullup on D+ reduces the chip current consumption and shorting D- to D+ in this mode (so both pins are high) reduces current to <10uA. By comparison, without these workarounds, current consumption was ~500uA at -10C, ~100uA at 25C and ~60 at +50C. Quite the opposite to what you would normally expect i.e. leakage increasing with higher temperature.
So I have 3 questions:
1. Does NXP know about this?
2. Why does the datasheet say the pins are pulled low?
3. Has anyone else had this problem?
And finally, I am posting this to help out anyone who might be having power consumption problems. I know it is difficult to find every last uA.