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SPI slave mode details

Question asked by Craig McQueen on Feb 19, 2018
Latest reply on Feb 26, 2018 by Craig McQueen

I have a number of questions about SPI slave mode on the LPC11U6x, which are not answered in the user manual. Most of them are concerned with the correct TX of data (which is more challenging for the slave side of SPI).

 

  • If the TX FIFO is empty, what is transmitted on MISO -- 0x00, 0xFF, or a repeat of the previous byte?
  • If SSEL is deasserted while the TX FIFO still contains data, is the TX FIFO flushed?
  • Can I flush the TX FIFO?
  • Can I preload the TX FIFO with data while SSEL line is idle?
  • Is it possible to detect TX underflow?
  • Can I get an interrupt as soon as the SSEL line is asserted? (so that I know I need to prepare data to be read). Either from the SSP, or from the PINT.
    • Is it possible to configure a pin for PINT if the pin is configured for a function other than GPIO? Or, would I need to connect the SSEL line to a second pin to provide the PINT functionality?

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