I have a question about WAIT4EOT_3 and WAIT4EOT_9 of i.MX6DQ reference manual.
There is a register IPUx_DMFC_GENERAL_1, that specify WAIT4EOT_3 and WAIT4EOT_9 for each FIFO#3 and FIFO#9.
Bit6-5 of IPUx_DMFC_GENERAL_1 , dmfc_burst_size_9 is specify Burst size of IDMAC's channel 44, that means FIFO#9 is for IDMAC 44.
However, in Table 37-23. Display port channels, IDMAC's channel number 44 is related to DMFC channel number 3.
What is for WAIT4EOT_9 and WAIT4EOT_3?