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IMX6 Solo LPDDR2 Calibration Failure

Question asked by Jarrod Cook on Feb 13, 2018
Latest reply on May 4, 2018 by Jarrod Cook

Hello,

We have created a custom board using an IMX6 Solo and a combination NAND/LPDDR2 chip (MT29RZ4B2DZZHHWD-18I).  We have just finished producing some prototypes and I have used the Register programming aid (V1.3) to setup a script for the DDR Stress Tester Tool (I have tried both V2.80 and V1.0.3).  I am connecting via the USB port and I am able to download into the part and I can even read and write individual registers using the DDR tool; however, I am unable to run either the Calibration or the Stress test successfully.  I am thinking this likely indicates some sort of layout issue, but wondered if someone could verify the following are correct:

 

  1. Init Script - It was generated using the script aid tool and I think i got all the values in there correct but i don't have a working Solo/Dual Lite board with LPDDR2 to test it with.  Script is attached.
  2. Circuit - There was this confusing table in the hardware document of how to map pins on the Solo for LPDDR3 instead of DDR3 and I am nervous that one of the non-data lines is incorrectly connected.

 

I just want to verify the above uncertainties aren't a problem before i head down the route of layout modifications and ordering new boards.  Thanks!  Oh here is the output from the DDR Test Tool:

 

============================================
DDR Stress Test (2.6.0)
Build: Jan 24 2018, 14:20:57
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.3
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x32000001
============================================

ARM Clock set to 800MHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is LPDDR2 in 1-channel mode.
Data width: 32, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 256MB
Density per channel: 256MB
============================================


0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x10000000: 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
memory read is done
addr=0x10000000,data=0xDEADBEEF

Success to write address 0x10000000

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x10000000: 0xDEADBEEF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
memory read is done
Current Temperature: 71
============================================

DDR Freq: 396 MHz

Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 0001:byte 0 fail.
result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x1111
ABS_OFFSET=0x04040404 result[01]=0x1111
ABS_OFFSET=0x08080808 result[02]=0x1111
ABS_OFFSET=0x0C0C0C0C result[03]=0x1111
ABS_OFFSET=0x10101010 result[04]=0x1111
ABS_OFFSET=0x14141414 result[05]=0x1111
ABS_OFFSET=0x18181818 result[06]=0x1111
ABS_OFFSET=0x1C1C1C1C result[07]=0x1111
ABS_OFFSET=0x20202020 result[08]=0x1111
ABS_OFFSET=0x24242424 result[09]=0x1111
ABS_OFFSET=0x28282828 result[0A]=0x1111
ABS_OFFSET=0x2C2C2C2C result[0B]=0x1111
ABS_OFFSET=0x30303030 result[0C]=0x1111
ABS_OFFSET=0x34343434 result[0D]=0x1111
ABS_OFFSET=0x38383838 result[0E]=0x1111
ABS_OFFSET=0x3C3C3C3C result[0F]=0x1111
ABS_OFFSET=0x40404040 result[10]=0x1111
ABS_OFFSET=0x44444444 result[11]=0x1111
ABS_OFFSET=0x48484848 result[12]=0x1111
ABS_OFFSET=0x4C4C4C4C result[13]=0x1111
ABS_OFFSET=0x50505050 result[14]=0x1111
ABS_OFFSET=0x54545454 result[15]=0x1111
ABS_OFFSET=0x58585858 result[16]=0x1111
ABS_OFFSET=0x5C5C5C5C result[17]=0x1111
ABS_OFFSET=0x60606060 result[18]=0x1111
ABS_OFFSET=0x64646464 result[19]=0x1111
ABS_OFFSET=0x68686868 result[1A]=0x1111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x1111
ABS_OFFSET=0x70707070 result[1C]=0x1111
ABS_OFFSET=0x74747474 result[1D]=0x1111
ABS_OFFSET=0x78787878 result[1E]=0x1111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x1111

ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

DDR Stress Test Iteration 1
Current Temperature: 71
============================================

DDR Freq: 297 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000140
Data was: 0x00000000
But pattern should match address
Error: failed to run stress test!!!

DDR Stress Test Iteration 1
Current Temperature: 70
============================================

DDR Freq: 297 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000220
Data was: 0x00000000
But pattern should match address
Error: failed to run stress test!!!

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