IMX6 Solo LPDDR2 Calibration Failure

[jcc273]

Hello,

We have created a custom board using an IMX6 Solo and a combination NAND/LPDDR2 chip (MT29RZ4B2DZZHHWD-18I).  We have just finished producing some prototypes and I have used the Register programming aid (V1.3) to setup a script for the DDR Stress Tester Tool (I have tried both V2.80 and V1.0.3).  I am connecting via the USB port and I am able to download into the part and I can even read and write individual registers using the DDR tool; however, I am unable to run either the Calibration or the Stress test successfully.  I am thinking this likely indicates some sort of layout issue, but wondered if someone could verify the following are correct:

1. Init Script - It was generated using the script aid tool and I think i got all the values in there correct but i don't have a working Solo/Dual Lite board with LPDDR2 to test it with.  Script is attached.
2. Circuit - There was this confusing table in the hardware document of how to map pins on the Solo for LPDDR3 instead of DDR3 and I am nervous that one of the non-data lines is incorrectly connected.

I just want to verify the above uncertainties aren't a problem before i head down the route of layout modifications and ordering new boards.  Thanks!  Oh here is the output from the DDR Test Tool:

============================================
DDR Stress Test (2.6.0)
Build: Jan 24 2018, 14:20:57
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.3
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x32000001
============================================

ARM Clock set to 800MHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is LPDDR2 in 1-channel mode.
Data width: 32, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 256MB
Density per channel: 256MB
============================================

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x10000000: 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
memory read is done
addr=0x10000000,data=0xDEADBEEF

Success to write address 0x10000000

0x0 0x4 0x8 0xC
----------------------------------------------------------------------------------------------------------------
0x10000000: 0xDEADBEEF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
memory read is done
Current Temperature: 71
============================================

DDR Freq: 396 MHz

Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 0001:byte 0 fail.
result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x1111
ABS_OFFSET=0x04040404 result[01]=0x1111
ABS_OFFSET=0x08080808 result[02]=0x1111
ABS_OFFSET=0x0C0C0C0C result[03]=0x1111
ABS_OFFSET=0x10101010 result[04]=0x1111
ABS_OFFSET=0x14141414 result[05]=0x1111
ABS_OFFSET=0x18181818 result[06]=0x1111
ABS_OFFSET=0x1C1C1C1C result[07]=0x1111
ABS_OFFSET=0x20202020 result[08]=0x1111
ABS_OFFSET=0x24242424 result[09]=0x1111
ABS_OFFSET=0x28282828 result[0A]=0x1111
ABS_OFFSET=0x2C2C2C2C result[0B]=0x1111
ABS_OFFSET=0x30303030 result[0C]=0x1111
ABS_OFFSET=0x34343434 result[0D]=0x1111
ABS_OFFSET=0x38383838 result[0E]=0x1111
ABS_OFFSET=0x3C3C3C3C result[0F]=0x1111
ABS_OFFSET=0x40404040 result[10]=0x1111
ABS_OFFSET=0x44444444 result[11]=0x1111
ABS_OFFSET=0x48484848 result[12]=0x1111
ABS_OFFSET=0x4C4C4C4C result[13]=0x1111
ABS_OFFSET=0x50505050 result[14]=0x1111
ABS_OFFSET=0x54545454 result[15]=0x1111
ABS_OFFSET=0x58585858 result[16]=0x1111
ABS_OFFSET=0x5C5C5C5C result[17]=0x1111
ABS_OFFSET=0x60606060 result[18]=0x1111
ABS_OFFSET=0x64646464 result[19]=0x1111
ABS_OFFSET=0x68686868 result[1A]=0x1111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x1111
ABS_OFFSET=0x70707070 result[1C]=0x1111
ABS_OFFSET=0x74747474 result[1D]=0x1111
ABS_OFFSET=0x78787878 result[1E]=0x1111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x1111

ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

DDR Stress Test Iteration 1
Current Temperature: 71
============================================

DDR Freq: 297 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000140
Data was: 0x00000000
But pattern should match address
Error: failed to run stress test!!!

DDR Stress Test Iteration 1
Current Temperature: 70
============================================

DDR Freq: 297 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000220
Data was: 0x00000000
But pattern should match address
Error: failed to run stress test!!!

[Yuri · Accepted solution]

Hello,

  Please look at my comments below.

1.

    For Your configuration only MMDC0 should be init-ed.

(

BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is LPDDR2 in 1-channel mode.
)

2.

 Scheme in general is correct, but strictly speaking, data bit swapping for LPDDR2

is not allowed.

https://community.nxp.com/message/571460 

Have a great day,

Yuri

------------------------------------------------------------------------------

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button. Thank you!

[jcc273]

Another quick note we also had the positive and negative clocks reversed.

[jcc273]

Yuri,

Thanks for the reply!  I greatly appreciate it!

1.  Alright so basically just remove anything from the script that sets up MMDC1, like the new attached version?  I still had to enable CS0 on MMDC1(0x021b4000) even though I'm only using MMDC0 otherwise things don't work at all.  (Still failed after the changes, assuming layout problems at this point).

2.  Okay as we redo the layout we will try to route them unswapped as best we can.  We are very tight on area and can only come out 1 side of the CPU, but we only have 1 LPDDR2 Chip and from what I am reading it seems that the restrictions are due only to the ability to read the mode register out of DQ0-7 and for driving MRR bursts on the least significant bit of each byte.  So does this mean as long as I don't bit or byte swap DQ[0:7] and i leave the least significant bit of each byte (0,8,16,24) in the correct spot i should be okay?  Meaning i could byte swap DQ[8:15],DQ[16:23],DQ[24:31] and i could bit swap bits 1-7 in within each byte group?

Thanks again!

-Jarrod

[Yuri]

Hello,

According to the discussion from the link below:

  Byte Group:

1. Byte Group 0 should not be swapped (for Mode Reg Read).

2. Byte Groups 1, 2 and 3 can be swapped in any order.

  As for Bits within Byte Groups

3. Byte Group 0 should not have bits rearranged (for Mode Reg Read data)

4. Byte Groups 1, 2 and 3 can have bits rearranged within them

  if manufacturer allows it (Micron drives DQ Calibration to all bits).

5. It would be technically more correct to keep bits 8, 16, and 24 as the

  LSB in each byte group.

Zynq LPDDR2 DQ Swap Question - Community Forums 

So, You are right: "this mean as long as I don't bit or byte swap DQ[0:7] and I leave the

least significant bit of each byte (0,8,16,24) in the correct spot it should be okay". 

Regards,

Yuri.

[jcc273]

Awesome!  Thanks for verifying Yuri!  So I guess we will fix DQ[0:7] and clean up our layout and then hopefully everything will work after that, since the rest of the schematics and configuration look good.  I will update this post after we get new boards.  Thanks for the the help Yuri!!!

-Jarrod