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Kinetis(MK22FN512xxx12) Flash Verification in Keil with J-link

Question asked by Jun-Young Lee on Feb 8, 2018
Latest reply on Feb 11, 2018 by Jun-Young Lee

Hello there. 

 

I need some wisdom about minor(?) problem.

 

My company's new project is based on MK22FN51VLH12 chip. (Kinetis thing as you know,)

 

IDE is Keil uVision V5 for some reasons.

Dev tool is Segger J-link lite. (a bundle thing I guess,)

Of course, the board is custom made.

 

When I build a project, it's fine.

When I flash the target, there is the problem.

 

I assume flash writing fine because chip running as normal. (GPIO, UART, etc. works fine.)

 

But when chip verification, it prints out like this in build log

 

I already heard there is some region in Flash which cannot access.

 

But in my opinion, if I choose the right flash algorithm, verification also should be fine, isn't it?

 

Did I miss something? Are there any more options should I adjust?

 

I add some info.

 

Thx for your opinion!

 

Have nice day 

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