Giuseppe Modugno

LPC1785 and SDRAM issue

Discussion created by Giuseppe Modugno on Feb 7, 2018
Latest reply on Feb 7, 2018 by jeremyzhou

I designed a custom 4-layers PCB with LPC1785 (208 pins) and SDRAM (MT48LC2M32B2, 512K x 32 x 4 Banks from Micron). The connections are the same as in EA 1788 dev board:

  • EMC_A[0:11] to A[11:0] of SDRAM
  • EMC_A12 not connected
  • EMC_A13 to BA0; EMC_A14 to BA1
  • EMC_D[31:0] to D[31:0] of SDRAM
  • EMC_DQM[3:0] to DQM[3:0] of SDRAM
  • EMC_CLK0 to CLK of SDRAM; EMC_CKE0 to CKE of SDRAM
  • EMC_CLK1 and EMC_CKE[3:1] not connected
  • EMC_WE, EMC_CAS, EMC_RAS to WE, CAS, RAS of SDRAM
  • EMC_DYCS0 to CS of SDRAM
  • EMC_DYCS[3:1] not connected

I started from the example periph_memtest found in LPCOpen v2.10. I only changed the function Board_SetupClocking() to avoid SPIFI clock configuration and to call Chip_SetupIrcClocking() instead of Chip_SetupXtalClocking() (actually the crystal isn't mounted on my board).

 

void Board_SetupClocking(void)
{
/* Enable PBOOST for CPU clock over 100MHz */
Chip_SYSCTL_EnableBoost();

//Chip_SetupXtalClocking();
Chip_SetupIrcClocking();

/* SPIFI clocking will be derived from Main PLL with a divider of 2 (60MHz) */
//Chip_Clock_SetSPIFIClockDiv(2);
//Chip_Clock_SetSPIFIClockSource(SYSCTL_SPIFICLKSRC_MAINPLL);

}

 

I also changed Board_SetupExtMemory() function commenting static memories configuration.

 

/* Setup external memories */
void Board_SetupExtMemory(void)
{
   /* Setup EMC Delays */
   /* Move all clock delays together */
   LPC_SYSCTL->EMCDLYCTL = (CLK0_DELAY) | (CLK0_DELAY << 8) | (CLK0_DELAY << 16 | (CLK0_DELAY << 24));

   /* Setup EMC Clock Divider for divide by 2 */
   /* Setup EMC clock for a divider of 2 from CPU clock. Enable EMC clock for
external memory setup of DRAM. */
   Chip_Clock_SetEMCClockDiv(SYSCTL_EMC_DIV2);
   Chip_SYSCTL_PeriphReset(SYSCTL_RESET_EMC);

 

   /* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
   Chip_EMC_Init(1, 0, 0);

   /* Init EMC Dynamic Controller */
   Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &IS42S32800D_config);

 

   /* Init EMC Static Controller CS0 */
   //Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &SST39VF320_config);

   /* Init EMC Static Controller CS1 */
   //Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &K9F1G_config);

 

   /* EMC Shift Control */
   LPC_SYSCTL->SCS |= 1;
}

 

I also changed the configuration structure of SDRAM to reflect the real memory configuration (512k x 32 x 4 banks):

 

STATIC const IP_EMC_DYN_CONFIG_T IS42S32800D_config = {
   EMC_NANOSECOND(64000000 / 4096),
   0x01, /* Command Delayed */
   3, /* tRP */
   7, /* tRAS */
   EMC_NANOSECOND(70), /* tSREX */
   EMC_CLOCK(0x01), /* tAPR */
   EMC_CLOCK(0x05), /* tDAL */
   EMC_NANOSECOND(12), /* tWR */
   EMC_NANOSECOND(60), /* tRC */
   EMC_NANOSECOND(60), /* tRFC */
   EMC_NANOSECOND(70), /* tXSR */
   EMC_NANOSECOND(12), /* tRRD */
   EMC_CLOCK(0x02), /* tMRD */
   {
      {
         EMC_ADDRESS_DYCS0, /* EA Board uses DYCS0 for SDRAM */
         2, /* RAS */

 

         EMC_DYN_MODE_WBMODE_PROGRAMMED |
         EMC_DYN_MODE_OPMODE_STANDARD |
         EMC_DYN_MODE_CAS_2
         EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
         EMC_DYN_MODE_BURST_LEN_4,

 

         EMC_DYN_CONFIG_DATA_BUS_32 |
         EMC_DYN_CONFIG_LPSDRAM |
         EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS | //EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS |
         EMC_DYN_CONFIG_MD_SDRAM
      },
      {0, 0, 0, 0},
      {0, 0, 0, 0},
      {0, 0, 0, 0}
   }
};

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