I am using Kenitis K10 Cortex m4 CPU on our board , when it was taken as a SMBUS slave device .
I checked all the registers of I2C and SMBUS , but still cannot find how this slave device check whether it is the final byte in the transfer from the master device, when it is in receive slave mode.
Could you know which bit in the registers means the slave device receives a stop signal? and would the STOP signal issue a individual interrupt ?
thanks a lot.