I'm currently working on the design of a board which uses a i.MX6UL + DDR3 RAM memory.
At the moment we selected a 1Gb DDR3 (x16), but we might change it to 2Gb in the future.
The only difference when switching between capacity is the number of address lines used:
- Only ADDR[0..12] for 1Gb
- ADDR[0..13] for 2Gb
- ADDR[0..14] for 4Gb
As unused ADDR lines are recommended to be NC, is it an issue if those lines are connected after all to ensure higher capacity compatibility?