i.MX6QP LVDS1 pixel clock

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i.MX6QP LVDS1 pixel clock

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alexk-windriver
Contributor III

I’d like to better understand the LVDS1 clocking mechanism.

I have booted Freescale's 4.1.15-1.2.0 Yocto BSP on i.MX6QP and dumped the registers:

CS2CDR

0x007192c1

ldb_di0_clk_sel =PLL2 PFD0

ldb_di1_clk_sel =PLL2 PFD0

CSCMR2

0x02b92c06

ldb_di0_ipu_div=1 (div by 7)

ldb_di1_ipu_div=1 (div by 7)

CCM_CCGR3

[CG7]

[CG6]

[CG5]

[CG4]

[CG3]

[CG2]

[CG1]

[CG0]

0x3ff3ccc0

ldb_di1_clk_en=11

ldb_di0_clk_en=00

ipu2_di1 clock=11

ipu2_di0 clock=00

ipu2_ipu_clock=11

ipu1_di1 clock=00

ipu1_di0 clock=00

ipu1_ipu_clock=00

CCM_CSCDR2

0x00011888

ipu2_di1 clock_sel = ldb_di1_clk

IOMUXC_GPR2

0x0000040c

CH1_MODE=11 (routed to DI1)

DI1_VS_POLARITY=1

IOMUXC_GPR3

0x01e00310

LVDS1_MUX_CTL=11

(source is IPU2 DI1 port)

 

Based on the above settings, it seems the LVDS1 pixel clock should be 352MHz/7 = 50.2857 MHz, is this correct?

Are there any other registers that I would need to setup in order to enable LVDS1 in non-Linux OS?

I am aware of the need to have proper settings for IOMUXC_*PAD* pins too.

 

Thanks

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joanxie
NXP TechSupport
NXP TechSupport

refer to the table as below,

pastedImage_1.png

one can get displa interface clock from 20-170MHZ, which depends what you need, if you need to set specific lvds, one need to add your own  in /drivers/video/mxc/ldb.c

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