I’d like to better understand the LVDS1 clocking mechanism.
I have booted Freescale's 4.1.15-1.2.0 Yocto BSP on i.MX6QP and dumped the registers:
ldb_di0_clk_sel =PLL2 PFD0
ldb_di1_clk_sel =PLL2 PFD0
ldb_di0_ipu_div=1 (div by 7)
ldb_di1_ipu_div=1 (div by 7)
ipu2_di1 clock_sel = ldb_di1_clk
CH1_MODE=11 (routed to DI1)
(source is IPU2 DI1 port)
Based on the above settings, it seems the LVDS1 pixel clock should be 352MHz/7 = 50.2857 MHz, is this correct?
Are there any other registers that I would need to setup in order to enable LVDS1 in non-Linux OS?
I am aware of the need to have proper settings for IOMUXC_*PAD* pins too.