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POR_B and JTAG_TRST_B / JLINK debug

Question asked by Lars Heinrichs on Feb 1, 2018
Latest reply on Feb 2, 2018 by Sinan Akman

Hello community,

 

 

I am wondering about the POR_B and JTAG_TRST_B signals.

On the SABRE board the POR_B signal is connected to anything related to reseting the system (PMIC, MX7, IO extender, watch dog, JTAG connector). But there are pretty much two exceptions:

  1. the JTAG_RST signal on the JTAG header is connected to POR_B using a shottky diode 
  2. JTAG_TRST_B on the SoC is not connected at all because of a non populated resistor

 

On my custom Hardware I used a shottky diode between the JTAG connector and POR_B as well but the SOC and JTAG connector have the signal JTAG_TRST_B connected on the PCB.

What are the effects of this connection?

 

I can see the two boards behave slightly different when attached to a segger jlink.
Custom Hardware:

Feature(s): GDB
Checking target voltage...
Target voltage: 1.81 V
Listening on TCP/IP port 2331
Connecting to target...
J-Link found 1 JTAG device, Total IRLen = 4
JTAG ID: 0x5BA00477 (Cortex-M4)
WARNING: CPU could not be halted
Halting target device failed. Trying again with reset
WARNING: CPU could not be halted
Failed to halt target device on connect
ERROR: Could not connect to target.

SABRE board:

Feature(s): GDB
Checking target voltage...
Target voltage: 3.32 V
Listening on TCP/IP port 2331
Connecting to target...ERROR: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0x5.
Could not find core in Coresight setup
ERROR: Could not connect to target.

May this be related to the difference in the reset signal?
What else may cause this behaviour?

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