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"System clock cycle" meaning of DC parameter table.

Question asked by Takayuki Ishii on Feb 1, 2018
Latest reply on Feb 5, 2018 by Takayuki Ishii

Hello community,

 

I have one question about DC parameter table of datasheet.

In datasheet IMX6DQAEC rev5 09/2017,  footnote 1 of Table 22 say that 

 

1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle.

 

I think that "system clock cycle" of this comment mean a XTALI input clock cycle.

So that is a calculate as following.

 

10% of the system clock cycle = 1/24MHz * 10/100 = 4.1nsec

 

Is ti correct?

 

Best regards,

Ishii.

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