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Fail to execute PIT timer 1 or timer 2 in core 1 for MPC5777C

Question asked by Sourabh Jain on Jan 31, 2018
Latest reply on Jul 31, 2018 by Emanuele Ghidoli



We are using S32 Design Studio.


S32 Design Studio for Power Architecture

Version: 1.2 
Build id: 170613

(c) Copyright Freescale Semiconductor 2016. All rights reserved. 
(c) Copyright NXP 2017.



MCU ==
evb == MPC5777C EVB 

debugger == Multilink universal fx

Operating System == Win7x64,Win8x64



i am genrating delay using PIT timer 1 in both core 0 and core 1. PIT timer working in core 0 successfully but in core 1 PIT timer is not working.

i also configured INTC_PSR regiester as shown below where i select interrupt request send to both processors.

but interrupt is generated only in core 0 not in core 1.


i also changes priority of interrupt in both core 0 and core 1 but its not working.


i also check by using PIT timer in core 0 and PIT timer 2 in core 1 but its also not working.


So can you please check that why interrupt is not generated in core 1. and also check that we can use PIT timer in core 1 or not?


here is code for initialization of PIT timer 1


void PIT1_Init(void)

/* LDVAL = peripheral clock -1 i.e peri_clck = 96MZ
* creates time interval of 500msec
PIT.TIMER[1].LDVAL.R = 192-1; //Timer Start Value
PIT.TIMER[1].TFLG.R = 0x00000001; //clear the TIF flag
PIT.TIMER[1].TCTRL.B.TIE = 1; //Interrupt will be requested whenever TIF is set
PIT.TIMER[1].TCTRL.B.TEN = 1; // start Timer