Robert Wynn


Discussion created by Robert Wynn on Jan 29, 2018
Latest reply on Feb 1, 2018 by Robert Wynn

I have a DEVKIT-S12G128, 8Mhz crystal. CodeWarrior 5.9.0. The issue I have is with the PWM. I have setup a 24Mhz bus clock and a 24kHz PWM (16bit) channel (10%duty) . Everything looks ok if you look at a few cycles of the PWM. After about 230ms the output STOPS and restarts in another 230ms.


// example devkit-s12g128 with 8MHz crystal
// output on pin PP1 (J2-01)
// 24khz pwm signal with a 10% duty cycle.
// After about 230ms the output STOPS. It restarts after about 230ms.
// At 1% duty the output stops after 22ms. It restarts after about 440ms


#include <hidef.h>  
#include "derivative.h"


void SetPEEmodeBUSCLK(byte _synr, byte _refdv, byte _postdiv);


void main(void)
  DDRP =0x02;
  SetPEEmodeBUSCLK(0x02, 0x80, 0x00);   // 24MHz BUSCLK from 8 MHZ oscclk, PEE mode
  PWME = 0x00;        // Disable all PWM channels
  PWMPOL =0xFF;       // All channels are high an go low
  PWMCLK = 0x00;      // All channels are clocked from A or B clock source
  PWMCLKAB = 0x00;    // Clock A is the source clock for all channels
  PWMPRCLK = 0x00;    // Clock A & B equal to BUS clock
  PWMCAE = 0x00;      // left aligned
  PWMCTL = 0x10;      // 0-1 concatenated to form 16-bit PWM
  PWMPER01 = 1000;    // PWM channel 01 period
  PWME = 0x02;        // Enable the channel
  PWMDTY01 = 100;     // set duty cycle for 01


void SetPEEmodeBUSCLK(byte _synr, byte _refdv, byte _postdiv)
 CPMUSYNR    = _synr;
 CPMUREFDIV  = _refdv;
 CPMUPOSTDIV = _postdiv;


 CPMUOSC_OSCE = 1; //enable external oscillator OSCE


  {// you can check for timeot here with error message report
  {// you can check for timeot here with error message report


  //--- select clocks --------------------
  CPMUCLKS = 0B10000011;                   // bus=fPLL/2; COP is clocked from OSCCLK
  if(CPMUCLKS != 0B10000011)               // After writing CPMUCLKS register, it is strongly recommended to read
  {                                       // back CPMUCLKS register to make sure that write of PLLSEL,
    asm nop;                             // RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful.