AnsweredAssumed Answered

iMX6UL no data on Ethernet fec2 ENET2 MII bus

Question asked by yvan labadie on Jan 29, 2018
Latest reply on Jun 12, 2019 by claudio@databyte.ch

Hello,

We have a custom board based on Armadeus OPOS6UL module (iMX6UL) version without wifi option.
We want to connect a PLC module ont the ENET2 MII bus (already using this modules on other hardwares/processors).

The PLC module acts as a Phy except that there is no MDIO, we specify a fixed-phy 100Mb full-duplex.

 

Problem is:

When we send data (ARP requests, ICMP...) from iMX to PLC: nothing goes out of the PLC module.

Register ENET2_RMON_T_PACKETS[0x2028204] correctly counts the number of packet to be sent.

Register ENET2_IEEE_T_FRAME_OK[0x202824c] says that all packets has been sent OK

With a scope we can see data signals moving on ENET2_TXDATA[0-3]...

 

In the other direction: Wen we send broadcast data (ARP requests) on the PLC network,but the iMX sees nothing.

we can see data on ENET2_RXDATA[0-3] .

Register ENET2_RMON_R_PACKETS[0x2028284] keep counting 0 packet received.

Except if we send a lot of data, it counts a few of them in error (ENET2_IEEE_R_CRC[0x20282d0] and  ENET2_IEEE_R_ALIGN[0x20282d4]).

 

ENET2_RX_CLK and ENET2_TX_CLK are 25MHz.

 

Here is the ethernet device tree configuration:


/* ethernet 2 */
&fec2 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2>;
        phy-mode = "mii";
        fixed-link {
                speed = <100>;
                full-duplex;
        };
};


&iomuxc {
        pinctrl_enet2: enet2grp {
               fsl,pins = <
                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x130b0 
                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x130b0 
                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x130b0 
                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x130b0 
                        MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x130b0 
                        MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x130b0
                        MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x130b0

                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
                        MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x1b0b0
                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 
                        MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0 
                        MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0 
                        MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b031 

                        MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x130b0 /* Phy to MAC */
                        MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x130b0 /* Phy to MAC */
                >;
        };
};

 

 

Does anyone have a clue or faced something similar?

Thanks in advance!

Outcomes